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| author | Marek Olšák <marek.olsak@amd.com> | 2015-11-08 13:34:44 +0100 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2015-11-13 19:54:42 +0100 |
| commit | b1c5f3faa9d7a227150b677469df1a5832236541 (patch) | |
| tree | 98630efa0fd53ffe5c0dc7140d9939400cc87a70 /src/gallium/drivers/radeonsi/si_hw_context.c | |
| parent | 2f5d911ba2b0d477bce80e4dd3ae4d9748c6f784 (diff) | |
| download | external_mesa3d-b1c5f3faa9d7a227150b677469df1a5832236541.zip external_mesa3d-b1c5f3faa9d7a227150b677469df1a5832236541.tar.gz external_mesa3d-b1c5f3faa9d7a227150b677469df1a5832236541.tar.bz2 | |
radeonsi: calculate optimal GS ring sizes to fix GS hangs on Tonga
I discovered that increasing the ESGS ring size fixes GS hangs on Tonga,
so let's do it properly.
There is now a separate init_config_gs_rings state that is not immutable,
because GS rings are resized when needed.
This also saves some memory. Most apps won't need more than 1MB
per ring per shader engine.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_hw_context.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_hw_context.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c index f28c11c..baa0229 100644 --- a/src/gallium/drivers/radeonsi/si_hw_context.c +++ b/src/gallium/drivers/radeonsi/si_hw_context.c @@ -165,6 +165,8 @@ void si_begin_new_cs(struct si_context *ctx) /* The CS initialization should be emitted before everything else. */ si_pm4_emit(ctx, ctx->init_config); + if (ctx->init_config_gs_rings) + si_pm4_emit(ctx, ctx->init_config_gs_rings); ctx->framebuffer.dirty_cbufs = (1 << 8) - 1; ctx->framebuffer.dirty_zsbuf = true; |