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| author | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2016-05-10 00:48:55 +0200 |
|---|---|---|
| committer | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2016-05-26 22:07:04 +0200 |
| commit | c49e68dc4bcc14cac529d1e3be5fe0090ed4d146 (patch) | |
| tree | 1629b96be90bd0f16ddb44cd1fba0754abd660f7 /src/gallium/drivers/radeonsi/si_shader.h | |
| parent | d9a0c54f6f9811cfe6411a0ed4af8a1086b01b9d (diff) | |
| download | external_mesa3d-c49e68dc4bcc14cac529d1e3be5fe0090ed4d146.zip external_mesa3d-c49e68dc4bcc14cac529d1e3be5fe0090ed4d146.tar.gz external_mesa3d-c49e68dc4bcc14cac529d1e3be5fe0090ed4d146.tar.bz2 | |
radeonsi: Add user SGPR for the layout of the offchip buffer.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_shader.h')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_shader.h | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_shader.h b/src/gallium/drivers/radeonsi/si_shader.h index 7b1cbf9..26be25e 100644 --- a/src/gallium/drivers/radeonsi/si_shader.h +++ b/src/gallium/drivers/radeonsi/si_shader.h @@ -107,7 +107,8 @@ enum { SI_LS_NUM_USER_SGPR, /* both TCS and TES */ - SI_SGPR_TCS_OUT_OFFSETS = SI_NUM_RESOURCE_SGPRS, + SI_SGPR_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_SGPRS, + SI_SGPR_TCS_OUT_OFFSETS, SI_SGPR_TCS_OUT_LAYOUT, SI_TES_NUM_USER_SGPR, @@ -147,11 +148,18 @@ enum { SI_PARAM_LS_OUT_LAYOUT = SI_PARAM_START_INSTANCE + 1, /* the other VS parameters are assigned dynamically */ + /* Layout of TCS outputs in the offchip buffer + * [0:8] = the number of patches per threadgroup. + * [9:15] = the number of output vertices per patch. + * [16:31] = the offset of per patch attributes in the buffer in bytes. + */ + SI_PARAM_TCS_OFFCHIP_LAYOUT = SI_NUM_RESOURCE_PARAMS, /* for TCS & TES */ + /* Offsets where TCS outputs and TCS patch outputs live in LDS: * [0:15] = TCS output patch0 offset / 16, max = NUM_PATCHES * 32 * 32 * [16:31] = TCS output patch0 offset for per-patch / 16, max = NUM_PATCHES*32*32* + 32*32 */ - SI_PARAM_TCS_OUT_OFFSETS = SI_NUM_RESOURCE_PARAMS, /* for TCS & TES */ + SI_PARAM_TCS_OUT_OFFSETS, /* for TCS & TES */ /* Layout of TCS outputs / TES inputs: * [0:12] = stride between output patches in dwords, num_outputs * num_vertices * 4, max = 32*32*4 |