diff options
author | Marek Olšák <marek.olsak@amd.com> | 2016-10-10 17:39:43 +0200 |
---|---|---|
committer | Marek Olšák <marek.olsak@amd.com> | 2016-10-12 18:29:40 +0200 |
commit | 65a4d55a9ff12b44655803da10112d3b1b42ce13 (patch) | |
tree | 8bb1900d52d1e8cbeb3649f7deb9acb5cb67bcae /src/gallium/drivers/radeonsi/si_state.c | |
parent | 87b06cab14c449e442be27650024f044e93c9a7c (diff) | |
download | external_mesa3d-65a4d55a9ff12b44655803da10112d3b1b42ce13.zip external_mesa3d-65a4d55a9ff12b44655803da10112d3b1b42ce13.tar.gz external_mesa3d-65a4d55a9ff12b44655803da10112d3b1b42ce13.tar.bz2 |
radeonsi: don't invalidate VMEM L1 for memory barriers for index buffers
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state.c')
-rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index ddf6cfe..34f3ed7 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3366,6 +3366,7 @@ static void si_texture_barrier(struct pipe_context *ctx) SI_CONTEXT_CS_PARTIAL_FLUSH; } +/* This only ensures coherency for shader image/buffer stores. */ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags) { struct si_context *sctx = (struct si_context *)ctx; @@ -3392,9 +3393,9 @@ static void si_memory_barrier(struct pipe_context *ctx, unsigned flags) } if (flags & PIPE_BARRIER_INDEX_BUFFER) { - sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1; - - /* Indices are read through TC L2 since VI. */ + /* Indices are read through TC L2 since VI. + * L1 isn't used. + */ if (sctx->screen->b.chip_class <= CIK) sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2; } |