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| author | Marek Olšák <marek.olsak@amd.com> | 2016-08-10 12:19:49 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2016-08-17 12:24:35 +0200 |
| commit | e722b90bc9dae7438cbd3beaff439f45e2470ccc (patch) | |
| tree | a4da827b7f30ff06c0d6a8bb27875d77fc0cb79f /src/gallium/drivers/radeonsi/si_state.c | |
| parent | 3de8ffe836ceee0d49dd6199df721633612528b6 (diff) | |
| download | external_mesa3d-e722b90bc9dae7438cbd3beaff439f45e2470ccc.zip external_mesa3d-e722b90bc9dae7438cbd3beaff439f45e2470ccc.tar.gz external_mesa3d-e722b90bc9dae7438cbd3beaff439f45e2470ccc.tar.bz2 | |
radeonsi: eliminate PS OUT[1] if dual src blending is off and CB1 is not bound
All VP DX9 ports benefit from this.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 94dbe4c..5d55448 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2350,17 +2350,6 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, vi_separate_dcc_start_query(ctx, rtex); } } - /* Set the second SPI format for possible dual-src blending. */ - if (i == 1 && surf) { - sctx->framebuffer.spi_shader_col_format |= - surf->spi_shader_col_format << (i * 4); - sctx->framebuffer.spi_shader_col_format_alpha |= - surf->spi_shader_col_format_alpha << (i * 4); - sctx->framebuffer.spi_shader_col_format_blend |= - surf->spi_shader_col_format_blend << (i * 4); - sctx->framebuffer.spi_shader_col_format_blend_alpha |= - surf->spi_shader_col_format_blend_alpha << (i * 4); - } if (state->zsbuf) { surf = (struct r600_surface*)state->zsbuf; |