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| author | Marek Olšák <marek.olsak@amd.com> | 2014-04-23 16:15:36 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2014-07-18 01:58:58 +0200 |
| commit | 09056b352d6de42d24decafdcd6819ad70dc98f1 (patch) | |
| tree | a01e2e6d914a09447e5106891d1164d994ce9a24 /src/gallium/drivers/radeonsi/si_state_draw.c | |
| parent | a66d9341393b9a82aa197e8bab942c6de1ecf02e (diff) | |
| download | external_mesa3d-09056b352d6de42d24decafdcd6819ad70dc98f1.zip external_mesa3d-09056b352d6de42d24decafdcd6819ad70dc98f1.tar.gz external_mesa3d-09056b352d6de42d24decafdcd6819ad70dc98f1.tar.bz2 | |
radeonsi: use an SGPR instead of VGT_INDX_OFFSET
The draw indirect packets cannot set VGT_INDX_OFFSET, they can only set user
data SGPRs. This is the only way to support start/index_bias with indirect
drawing.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state_draw.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 01564eb..0007a70 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -426,14 +426,8 @@ static bool si_update_draw_info_state(struct si_context *sctx, } si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim); - si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, - info->indexed ? info->index_bias : info->start); si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index); si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart); - si_pm4_set_reg(pm4, SI_SGPR_START_INSTANCE * 4 + - (sctx->gs_shader ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : - R_00B130_SPI_SHADER_USER_DATA_VS_0), - info->start_instance); if (prim == V_008958_DI_PT_LINELIST) ls_mask = 1; @@ -730,6 +724,8 @@ static void si_state_draw(struct si_context *sctx, const struct pipe_draw_info *info, const struct pipe_index_buffer *ib) { + unsigned sh_base_reg = (sctx->gs_shader ? R_00B330_SPI_SHADER_USER_DATA_ES_0 : + R_00B130_SPI_SHADER_USER_DATA_VS_0); struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx); if (pm4 == NULL) @@ -791,6 +787,13 @@ static void si_state_draw(struct si_context *sctx, si_pm4_cmd_add(pm4, info->instance_count); si_pm4_cmd_end(pm4, sctx->b.predicate_drawing); + if (!info->indirect) { + si_pm4_set_reg(pm4, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, + info->indexed ? info->index_bias : info->start); + si_pm4_set_reg(pm4, sh_base_reg + SI_SGPR_START_INSTANCE * 4, + info->start_instance); + } + if (info->indexed) { uint32_t max_size = (ib->buffer->width0 - ib->offset) / sctx->index_buffer.index_size; |