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| author | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2016-04-02 11:37:06 +0200 |
|---|---|---|
| committer | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2016-04-19 18:10:32 +0200 |
| commit | 41d79bcbfa64f6f72b0090e12838073983ea6e5b (patch) | |
| tree | dc0f92767948ce8d7086fdd4cb0652e0c330f575 /src/gallium/drivers/radeonsi/si_state_draw.c | |
| parent | 7a92c0842892bf55a82b7d95ab5a3b7dfbb83407 (diff) | |
| download | external_mesa3d-41d79bcbfa64f6f72b0090e12838073983ea6e5b.zip external_mesa3d-41d79bcbfa64f6f72b0090e12838073983ea6e5b.tar.gz external_mesa3d-41d79bcbfa64f6f72b0090e12838073983ea6e5b.tar.bz2 | |
radeonsi: clean up compute flush
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state_draw.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 23 |
1 files changed, 8 insertions, 15 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 232f7a5..15d58d4 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -607,8 +607,6 @@ void si_emit_cache_flush(struct si_context *si_ctx, struct r600_atom *atom) struct r600_common_context *sctx = &si_ctx->b; struct radeon_winsys_cs *cs = sctx->gfx.cs; uint32_t cp_coher_cntl = 0; - uint32_t compute = - PKT3_SHADER_TYPE_S(!!(sctx->flags & SI_CONTEXT_FLAG_COMPUTE)); /* SI has a bug that it always flushes ICACHE and KCACHE if either * bit is set. An alternative way is to write SQC_CACHES, but that @@ -645,7 +643,7 @@ void si_emit_cache_flush(struct si_context *si_ctx, struct r600_atom *atom) /* Necessary for DCC */ if (sctx->chip_class >= VI) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0) | compute); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) | EVENT_INDEX(5)); radeon_emit(cs, 0); @@ -660,22 +658,17 @@ void si_emit_cache_flush(struct si_context *si_ctx, struct r600_atom *atom) } if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); /* needed for wait for idle in SURFACE_SYNC */ assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB); } if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); /* needed for wait for idle in SURFACE_SYNC */ assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB); } - if (sctx->flags & SI_CONTEXT_FLUSH_WITH_INV_L2) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); - radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH) | EVENT_INDEX(7) | - EVENT_WRITE_INV_L2); - } /* Wait for shader engines to go idle. * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait @@ -684,25 +677,25 @@ void si_emit_cache_flush(struct si_context *si_ctx, struct r600_atom *atom) if (!(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB))) { if (sctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); } else if (sctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); } } if (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4))); } /* VGT state synchronization. */ if (sctx->flags & SI_CONTEXT_VGT_FLUSH) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); } if (sctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) { - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0) | compute); + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0)); } |