diff options
| author | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2016-07-14 16:21:52 +0200 |
|---|---|---|
| committer | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2016-07-16 13:02:37 +0200 |
| commit | 6f73c7595fab450ae9fd1af67aaed322bca02ee0 (patch) | |
| tree | 10019cb1fa52a6126e1f03d19e1088e3328d4c18 /src/gallium/drivers/radeonsi/si_state_draw.c | |
| parent | b89d0df5351eea1f26c6890dcdff7c0e38424ee1 (diff) | |
| download | external_mesa3d-6f73c7595fab450ae9fd1af67aaed322bca02ee0.zip external_mesa3d-6f73c7595fab450ae9fd1af67aaed322bca02ee0.tar.gz external_mesa3d-6f73c7595fab450ae9fd1af67aaed322bca02ee0.tar.bz2 | |
radeonsi: remove the DRAW_PREAMBLE packet
According to firmware guys, the new sequence that we added for Polaris should
work on all CIK parts, and should actually be faster on some parts.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state_draw.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index a596bd8..24fa682 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -478,15 +478,10 @@ static void si_emit_draw_registers(struct si_context *sctx, if (prim != sctx->last_prim || ia_multi_vgt_param != sctx->last_multi_vgt_param || ls_hs_config != sctx->last_ls_hs_config) { - if (sctx->b.family >= CHIP_POLARIS10) { + if (sctx->b.chip_class >= CIK) { radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param); radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2, ls_hs_config); radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim); - } else if (sctx->b.chip_class >= CIK) { - radeon_emit(cs, PKT3(PKT3_DRAW_PREAMBLE, 2, 0)); - radeon_emit(cs, prim); /* VGT_PRIMITIVE_TYPE */ - radeon_emit(cs, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */ - radeon_emit(cs, ls_hs_config); /* VGT_LS_HS_CONFIG */ } else { radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim); radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param); |