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| author | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2016-05-10 00:48:55 +0200 |
|---|---|---|
| committer | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2016-05-26 22:07:04 +0200 |
| commit | c49e68dc4bcc14cac529d1e3be5fe0090ed4d146 (patch) | |
| tree | 1629b96be90bd0f16ddb44cd1fba0754abd660f7 /src/gallium/drivers/radeonsi/si_state_draw.c | |
| parent | d9a0c54f6f9811cfe6411a0ed4af8a1086b01b9d (diff) | |
| download | external_mesa3d-c49e68dc4bcc14cac529d1e3be5fe0090ed4d146.zip external_mesa3d-c49e68dc4bcc14cac529d1e3be5fe0090ed4d146.tar.gz external_mesa3d-c49e68dc4bcc14cac529d1e3be5fe0090ed4d146.tar.bz2 | |
radeonsi: Add user SGPR for the layout of the offchip buffer.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state_draw.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index dab0dcc..e14a1c9 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -108,6 +108,7 @@ static void si_emit_derived_tess_state(struct si_context *sctx, unsigned input_patch_size, output_patch_size, output_patch0_offset; unsigned perpatch_output_offset, lds_size, ls_rsrc2; unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets; + unsigned offchip_layout; *num_patches = 1; /* TODO: calculate this */ @@ -183,6 +184,8 @@ static void si_emit_derived_tess_state(struct si_context *sctx, ((output_vertex_size / 4) << 13); tcs_out_offsets = (output_patch0_offset / 16) | ((perpatch_output_offset / 16) << 16); + offchip_layout = (pervertex_output_patch_size * *num_patches << 16) | + (num_tcs_output_cp << 9) | *num_patches; /* Set them for LS. */ radeon_set_sh_reg(cs, @@ -191,13 +194,15 @@ static void si_emit_derived_tess_state(struct si_context *sctx, /* Set them for TCS. */ radeon_set_sh_reg_seq(cs, - R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OUT_OFFSETS * 4, 3); + R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4); + radeon_emit(cs, offchip_layout); radeon_emit(cs, tcs_out_offsets); radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26)); radeon_emit(cs, tcs_in_layout); /* Set them for TES. */ - radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OUT_OFFSETS * 4, 2); + radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3); + radeon_emit(cs, offchip_layout); radeon_emit(cs, tcs_out_offsets); radeon_emit(cs, tcs_out_layout | (num_tcs_output_cp << 26)); } |