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| author | Marek Olšák <marek.olsak@amd.com> | 2016-10-11 23:19:46 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2016-10-13 19:00:51 +0200 |
| commit | d4d9ec55c589156df4edc227a86b4a8c41048d58 (patch) | |
| tree | 646cdd6806f7a311c7e8a1403d5e715a79386af7 /src/gallium/drivers/radeonsi/si_state_draw.c | |
| parent | a077185ea9d685967844b68aa09da6bd8aa430da (diff) | |
| download | external_mesa3d-d4d9ec55c589156df4edc227a86b4a8c41048d58.zip external_mesa3d-d4d9ec55c589156df4edc227a86b4a8c41048d58.tar.gz external_mesa3d-d4d9ec55c589156df4edc227a86b4a8c41048d58.tar.bz2 | |
radeonsi: implement TC-compatible HTILE
so that decompress blits aren't needed and depth texturing needs less
memory bandwidth.
Z16 and Z24 are promoted to Z32_FLOAT by the driver, because TC-compatible
HTILE only supports Z32_FLOAT. This doubles memory footprint for Z16.
The format promotion is not visible to state trackers.
This is part of TC-compatible renderbuffer compression, which has 3 parts:
DCC, HTILE, FMASK. Only TC-compatible FMASK compression is missing now.
I don't see a measurable increase in performance though.
(I tested Talos Principle and DiRT: Showdown, the latter is improved by
0.5%, which is almost noise, and it originally used layered Z16,
so at least we know that Z16 promoted to Z32F isn't slower now)
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state_draw.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index c14e852..d18137b 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1118,7 +1118,8 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) struct pipe_surface *surf = sctx->framebuffer.state.zsbuf; struct r600_texture *rtex = (struct r600_texture *)surf->texture; - rtex->dirty_level_mask |= 1 << surf->u.tex.level; + if (!rtex->tc_compatible_htile) + rtex->dirty_level_mask |= 1 << surf->u.tex.level; if (rtex->surface.flags & RADEON_SURF_SBUFFER) rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level; |