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| author | Marek Olšák <marek.olsak@amd.com> | 2016-04-18 22:16:54 +0200 |
|---|---|---|
| committer | Marek Olšák <marek.olsak@amd.com> | 2016-04-22 01:14:13 +0200 |
| commit | 1378487fb4a0fe35779ead32b1ecd5467e3ba1c6 (patch) | |
| tree | cd3aa7ac8c2656f10f10de77fdad55116c80086d /src/gallium/drivers/radeonsi/si_state_shaders.c | |
| parent | 4ff8cbb0d8c483cc91cad3494cd1db572dcd51ee (diff) | |
| download | external_mesa3d-1378487fb4a0fe35779ead32b1ecd5467e3ba1c6.zip external_mesa3d-1378487fb4a0fe35779ead32b1ecd5467e3ba1c6.tar.gz external_mesa3d-1378487fb4a0fe35779ead32b1ecd5467e3ba1c6.tar.bz2 | |
radeonsi: rename and rearrange RW buffer slots
- use an enum
- use a unique slot number regardless of the shader stage
(the per-stage slots will go away for RW buffers)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_state_shaders.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_shaders.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 49e688a..5c923cb 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -1565,15 +1565,15 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx) /* Set ring bindings. */ if (sctx->esgs_ring) { - si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS, + si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_ES_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, true, true, 4, 64, 0); - si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS, + si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, false, false, 0, 0, 0); } if (sctx->gsvs_ring) - si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS, + si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_VS_RING_GSVS, sctx->gsvs_ring, 0, sctx->gsvs_ring->width0, false, false, 0, 0, 0); return true; @@ -1589,22 +1589,22 @@ static void si_update_gsvs_ring_bindings(struct si_context *sctx) sctx->last_gsvs_itemsize = gsvs_itemsize; - si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS, + si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_GSVS0, sctx->gsvs_ring, gsvs_itemsize, 64, true, true, 4, 16, 0); offset = gsvs_itemsize * 64; - si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_1, + si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_GSVS1, sctx->gsvs_ring, gsvs_itemsize, 64, true, true, 4, 16, offset); offset = (gsvs_itemsize * 2) * 64; - si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_2, + si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_GSVS2, sctx->gsvs_ring, gsvs_itemsize, 64, true, true, 4, 16, offset); offset = (gsvs_itemsize * 3) * 64; - si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_3, + si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_GSVS3, sctx->gsvs_ring, gsvs_itemsize, 64, true, true, 4, 16, offset); } @@ -1793,7 +1793,7 @@ static void si_init_tess_factor_ring(struct si_context *sctx) si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL); si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL, - SI_RING_TESS_FACTOR, sctx->tf_ring, 0, + SI_HS_RING_TESS_FACTOR, sctx->tf_ring, 0, sctx->tf_ring->width0, false, false, 0, 0, 0); } |