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| author | Eric Anholt <eric@anholt.net> | 2016-07-26 17:31:44 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2016-08-22 11:52:26 -0700 |
| commit | e8378fee0c20ecd26451c079c725420077606cb9 (patch) | |
| tree | 3603185648555d9e8a7a70efa52a79f2f97fd629 /src/gallium/drivers/vc4/vc4_nir_lower_io.c | |
| parent | 475ce61d1aa0fb06202511b4ea8ad9bd1fab64d0 (diff) | |
| download | external_mesa3d-e8378fee0c20ecd26451c079c725420077606cb9.zip external_mesa3d-e8378fee0c20ecd26451c079c725420077606cb9.tar.gz external_mesa3d-e8378fee0c20ecd26451c079c725420077606cb9.tar.bz2 | |
nir: Define system values for vc4's blending-lowering arguments.
In the GLSL-to-NIR conversion of VC4, I had a bit of trouble with what I
was calling the "state uniforms" that I was putting into the NIR fighting
with its other lowering passes. Instead of using magic uniform base
numbers in the backend, follow the lead of load_user_clip_plane and just
define system values for them.
v2: Fix unintended change to channel_num, drop unspecified const_index
value on blend_const_color_r_float.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/gallium/drivers/vc4/vc4_nir_lower_io.c')
| -rw-r--r-- | src/gallium/drivers/vc4/vc4_nir_lower_io.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/gallium/drivers/vc4/vc4_nir_lower_io.c b/src/gallium/drivers/vc4/vc4_nir_lower_io.c index 3d08b64..d61c95a 100644 --- a/src/gallium/drivers/vc4/vc4_nir_lower_io.c +++ b/src/gallium/drivers/vc4/vc4_nir_lower_io.c @@ -342,11 +342,13 @@ vc4_nir_lower_uniform(struct vc4_compile *c, nir_builder *b, intr_comp->num_components = 1; nir_ssa_dest_init(&intr_comp->instr, &intr_comp->dest, 1, 32, NULL); - /* Convert the uniform offset to bytes. If it happens to be a - * constant, constant-folding will clean up the shift for us. + /* Convert the uniform offset to bytes. If it happens + * to be a constant, constant-folding will clean up + * the shift for us. */ nir_intrinsic_set_base(intr_comp, - nir_intrinsic_base(intr) * 16 + i * 4); + nir_intrinsic_base(intr) * 16 + + i * 4); intr_comp->src[0] = nir_src_for_ssa(nir_ishl(b, intr->src[0].ssa, |