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| author | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2016-03-19 15:16:50 +0100 |
|---|---|---|
| committer | Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> | 2016-04-19 18:31:23 +0200 |
| commit | 464cef5b06e65aa740704e4adac68b7f5fee1b88 (patch) | |
| tree | 875b7715cf4db7bd7ab224213f9e34022a4b3bed /src/gallium/drivers | |
| parent | 1f32d5d59fff7a4ef42cd2811ef4116c5827b9a0 (diff) | |
| download | external_mesa3d-464cef5b06e65aa740704e4adac68b7f5fee1b88.zip external_mesa3d-464cef5b06e65aa740704e4adac68b7f5fee1b88.tar.gz external_mesa3d-464cef5b06e65aa740704e4adac68b7f5fee1b88.tar.bz2 | |
radeonsi: enable TGSI support cap for compute shaders
v2: Use chip_class instead of family.
v3: Check kernel version for SI.
v4: Preemptively allow amdgpu winsys for SI.
Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Diffstat (limited to 'src/gallium/drivers')
| -rw-r--r-- | src/gallium/drivers/radeon/r600_pipe_common.c | 21 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.c | 16 |
2 files changed, 30 insertions, 7 deletions
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c index a8660f2..9ed6da6 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.c +++ b/src/gallium/drivers/radeon/r600_pipe_common.c @@ -646,23 +646,34 @@ static int r600_get_compute_param(struct pipe_screen *screen, uint64_t *grid_size = ret; grid_size[0] = 65535; grid_size[1] = 65535; - grid_size[2] = 1; + grid_size[2] = 65535; } return 3 * sizeof(uint64_t) ; case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE: if (ret) { uint64_t *block_size = ret; - block_size[0] = 256; - block_size[1] = 256; - block_size[2] = 256; + if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 && + ir_type == PIPE_SHADER_IR_TGSI) { + block_size[0] = 2048; + block_size[1] = 2048; + block_size[2] = 2048; + } else { + block_size[0] = 256; + block_size[1] = 256; + block_size[2] = 256; + } } return 3 * sizeof(uint64_t); case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: if (ret) { uint64_t *max_threads_per_block = ret; - *max_threads_per_block = 256; + if (rscreen->chip_class >= SI && HAVE_LLVM >= 0x309 && + ir_type == PIPE_SHADER_IR_TGSI) + *max_threads_per_block = 2048; + else + *max_threads_per_block = 256; } return sizeof(uint64_t); diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index dabd28a..17d59b6 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -473,6 +473,8 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param) static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param) { + struct si_screen *sscreen = (struct si_screen *)pscreen; + switch(shader) { case PIPE_SHADER_FRAGMENT: @@ -490,9 +492,19 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu case PIPE_SHADER_CAP_PREFERRED_IR: return PIPE_SHADER_IR_NATIVE; - case PIPE_SHADER_CAP_SUPPORTED_IRS: - return 0; + case PIPE_SHADER_CAP_SUPPORTED_IRS: { + int ir = 1 << PIPE_SHADER_IR_NATIVE; + /* Old kernels disallowed some register writes for SI + * that are used for indirect dispatches. */ + if (HAVE_LLVM >= 0x309 && (sscreen->b.chip_class >= CIK || + sscreen->b.info.drm_major == 3 || + (sscreen->b.info.drm_major == 2 && + sscreen->b.info.drm_minor >= 45))) + ir |= 1 << PIPE_SHADER_IR_TGSI; + + return ir; + } case PIPE_SHADER_CAP_DOUBLES: return HAVE_LLVM >= 0x0307; |