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| author | Lionel Landwerlin <lionel.g.landwerlin@intel.com> | 2016-09-09 11:22:59 +0100 |
|---|---|---|
| committer | Lionel Landwerlin <lionel.g.landwerlin@intel.com> | 2016-09-20 10:47:21 +0100 |
| commit | 792d77165be40691d0c3b6dc025a792cb076109e (patch) | |
| tree | c281c11e55d3a53d369dbcce1f8ccae388dd8cca /src/gallium/state_trackers/omx | |
| parent | 0301858a316af7d831655778cf69bc49b12ee6ac (diff) | |
| download | external_mesa3d-792d77165be40691d0c3b6dc025a792cb076109e.zip external_mesa3d-792d77165be40691d0c3b6dc025a792cb076109e.tar.gz external_mesa3d-792d77165be40691d0c3b6dc025a792cb076109e.tar.bz2 | |
aubinator: add a custom handler for immediate register load
Transforming this :
0x00c77084: 0x11000001: MI_LOAD_REGISTER_IMM
0x00c77088: 0x0000b020 : Dword 1
Register Offset: 0x0000b020
0x00c7708c: 0x00880038 : Dword 2
Data DWord: 8912952
Into this:
0x007880f0: 0x11000001: MI_LOAD_REGISTER_IMM
0x007880f4: 0x0000b020 : Dword 1
Register Offset: 0x0000b020
0x007880f8: 0x00080040 : Dword 2
Data DWord: 524352
register L3CNTLREG2 (0xb020) : 0x80040
SLM Enable: 0
URB Allocation: 32
URB Low Bandwidth: 0
RO Allocation: 32
RO Low Bandwidth: 0
DC Allocation: 0
DC Low Bandwidth: 0
v2: Drop unused arguments (Sirisha)
Print out register name
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Diffstat (limited to 'src/gallium/state_trackers/omx')
0 files changed, 0 insertions, 0 deletions