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author | Marek Olšák <marek.olsak@amd.com> | 2016-01-30 02:29:32 +0100 |
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committer | Marek Olšák <marek.olsak@amd.com> | 2016-02-05 17:28:40 +0100 |
commit | 276621da451ae93321de05bf63baaf20ee2f32ca (patch) | |
tree | 8d24d919cde32089a4979d85f0649510db6e84b8 /src/gallium/winsys | |
parent | 294ec530c9829aead97487b1feb06361ef97cc2d (diff) | |
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gallium/radeon: set num_banks in the winsys
amdgpu doesn't have to set this, because radeonsi gets it from tile mode
arrays by default.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Diffstat (limited to 'src/gallium/winsys')
-rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index b97ccfd..f857a14 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -385,6 +385,11 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws) radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL, &ws->info.r600_tiling_config); + ws->info.r600_num_banks = + ws->info.chip_class >= EVERGREEN ? + 4 << ((ws->info.r600_tiling_config & 0xf0) >> 4) : + 4 << ((ws->info.r600_tiling_config & 0x30) >> 4); + if (ws->info.drm_minor >= 11) { radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL, &ws->info.num_tile_pipes); |