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| author | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2016-09-09 11:49:18 +0200 |
|---|---|---|
| committer | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2016-09-27 16:45:05 +0200 |
| commit | 6d89a4067627fdf568c6c4e3d9a201fd45d5352b (patch) | |
| tree | 0ba77efad5bc9db0bd42a4414d1c194334a5ed3f /src/gallium/winsys | |
| parent | e703f71ebdf91938c83f47c898f1da058ce0ac32 (diff) | |
| download | external_mesa3d-6d89a4067627fdf568c6c4e3d9a201fd45d5352b.zip external_mesa3d-6d89a4067627fdf568c6c4e3d9a201fd45d5352b.tar.gz external_mesa3d-6d89a4067627fdf568c6c4e3d9a201fd45d5352b.tar.bz2 | |
gallium/radeon: add RADEON_FLAG_HANDLE
When passed to winsys->buffer_create, this flag will indicate that we require
a buffer that maps 1:1 with a kernel buffer handle.
This is currently set for all textures, since textures can potentially be
exported to other processes. This is not a huge loss, since the main purpose
of this patch series is to deal with applications that allocate many small
buffers.
A hypothetical application with tons of tiny textures might still benefit
from not setting this flag, but that's not a use case I'm worried about
just now.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Diffstat (limited to 'src/gallium/winsys')
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 3 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 3 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 2 |
3 files changed, 7 insertions, 1 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c index 5b099b0..0dbd0fb 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c @@ -508,6 +508,9 @@ amdgpu_bo_create(struct radeon_winsys *rws, struct amdgpu_winsys_bo *bo; unsigned usage = 0, pb_cache_bucket; + /* This flag is irrelevant for the cache. */ + flags &= ~RADEON_FLAG_HANDLE; + /* Align size to page size. This is the minimum alignment for normal * BOs. Aligning this here helps the cached bufmgr. Especially small BOs, * like constant/uniform buffers, can benefit from better and more reuse. diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c index 5db2061..db92035 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c @@ -750,6 +750,9 @@ radeon_winsys_bo_create(struct radeon_winsys *rws, if (size > UINT_MAX) return NULL; + /* This flag is irrelevant for the cache. */ + flags &= ~RADEON_FLAG_HANDLE; + /* Align size to page size. This is the minimum alignment for normal * BOs. Aligning this here helps the cached bufmgr. Especially small BOs, * like constant/uniform buffers, can benefit from better and more reuse. diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c index c4933f0..a3b03be 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c @@ -620,7 +620,7 @@ radeon_cs_create_fence(struct radeon_winsys_cs *rcs) /* Create a fence, which is a dummy BO. */ fence = cs->ws->base.buffer_create(&cs->ws->base, 1, 1, - RADEON_DOMAIN_GTT, 0); + RADEON_DOMAIN_GTT, RADEON_FLAG_HANDLE); /* Add the fence as a dummy relocation. */ cs->ws->base.cs_add_buffer(rcs, fence, RADEON_USAGE_READWRITE, RADEON_DOMAIN_GTT, |