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authorNicolai Hähnle <nicolai.haehnle@amd.com>2016-06-30 20:04:54 +0200
committerNicolai Hähnle <nicolai.haehnle@amd.com>2016-07-06 10:43:52 +0200
commit7000dfd5c36dcfcc493e149e5aa5b4124d814d8a (patch)
tree62e7aef18be18f040a822a658564ded19c8bb275 /src/gallium/winsys
parent68fe270e71cafcaa23825442228f03f269598476 (diff)
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gallium/radeon: add depth/stencil_adjusted output to surface computation
This fixes a rare bug with stencil texturing -- seen on Polaris and Tonga, though it's basically a function of the memory configuration so could affect other parts as well. Fixes piglit "unaligned-blit * stencil downsample" and various "fbo-depth-array *stencil*" tests. Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Diffstat (limited to 'src/gallium/winsys')
-rw-r--r--src/gallium/winsys/amdgpu/drm/amdgpu_surface.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index dd033e0..cafa75d 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -454,6 +454,10 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
if (r)
return r;
+ /* DB uses the depth pitch for both stencil and depth. */
+ if (surf->stencil_level[level].nblk_x != surf->level[level].nblk_x)
+ surf->stencil_adjusted = true;
+
if (level == 0) {
/* For 2D modes only. */
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {