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| author | Michel Dänzer <michel.daenzer@amd.com> | 2014-10-08 16:01:47 +0900 |
|---|---|---|
| committer | Michel Dänzer <michel@daenzer.net> | 2014-10-15 16:26:14 +0900 |
| commit | 87da286755ea09b6efab591a124c261fde890ba8 (patch) | |
| tree | 9fee5a861f91b5f8044ff73771f59d1ddef6e7c4 /src/gallium | |
| parent | 3ede67a4c6d77892296ffc5568ddf3accaa1af99 (diff) | |
| download | external_mesa3d-87da286755ea09b6efab591a124c261fde890ba8.zip external_mesa3d-87da286755ea09b6efab591a124c261fde890ba8.tar.gz external_mesa3d-87da286755ea09b6efab591a124c261fde890ba8.tar.bz2 | |
r600g,radeonsi: Use staging texture for transfers if any miplevel is tiled
We set the NO_CPU_ACCESS flag for BO allocation in that case, so direct CPU
access may not work.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeon/r600_texture.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index 17aca01..13df495 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -924,7 +924,7 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx, * the CPU is much happier reading out of cached system memory * than uncached VRAM. */ - if (rtex->surface.level[level].mode >= RADEON_SURF_MODE_1D) + if (rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) use_staging_texture = TRUE; /* Untiled buffers in VRAM, which is slow for CPU reads */ |