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| author | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2016-08-08 15:54:50 +0200 |
|---|---|---|
| committer | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2016-08-09 15:56:04 +0200 |
| commit | b6c71d37c760242998a8e75b49c38134401eedd5 (patch) | |
| tree | 5d4ad4cfa2f64330e293e106f1fe6da1e0e6d048 /src/gallium | |
| parent | 8dbf2a857008599a9432d64c1363c5a1139e6acd (diff) | |
| download | external_mesa3d-b6c71d37c760242998a8e75b49c38134401eedd5.zip external_mesa3d-b6c71d37c760242998a8e75b49c38134401eedd5.tar.gz external_mesa3d-b6c71d37c760242998a8e75b49c38134401eedd5.tar.bz2 | |
radeonsi: program the DRAWID SGPR
Note that for indirect draws, the new MULTI firmware packets are required.
There's also no need to reset last_{start_instance,sh_base_reg}, since
resetting last_base_vertex is sufficient.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.h | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 8 |
2 files changed, 7 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 9e6bd78..f6535cf 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -308,6 +308,7 @@ struct si_context { /* Emitted draw state. */ int last_base_vertex; int last_start_instance; + int last_drawid; int last_sh_base_reg; int last_primitive_restart_en; int last_restart_index; @@ -414,8 +415,6 @@ static inline void si_invalidate_draw_sh_constants(struct si_context *sctx) { sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN; - sctx->last_start_instance = -1; /* reset to an unknown value */ - sctx->last_sh_base_reg = -1; /* reset to an unknown value */ } static inline void diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 3147311..d518d42 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -591,13 +591,16 @@ static void si_emit_draw_packets(struct si_context *sctx, if (base_vertex != sctx->last_base_vertex || sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN || info->start_instance != sctx->last_start_instance || + info->drawid != sctx->last_drawid || sh_base_reg != sctx->last_sh_base_reg) { - radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2); + radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3); radeon_emit(cs, base_vertex); radeon_emit(cs, info->start_instance); + radeon_emit(cs, info->drawid); sctx->last_base_vertex = base_vertex; sctx->last_start_instance = info->start_instance; + sctx->last_drawid = info->drawid; sctx->last_sh_base_reg = sh_base_reg; } } else { @@ -647,7 +650,8 @@ static void si_emit_draw_packets(struct si_context *sctx, radeon_emit(cs, info->indirect_offset); radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2); radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2); - radeon_emit(cs, 0); /* draw_index */ + radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) | + S_2C3_DRAW_INDEX_ENABLE(1)); radeon_emit(cs, 1); /* count */ radeon_emit(cs, 0); /* count_addr -- disabled */ radeon_emit(cs, 0); |