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| author | Tom Stellard <thomas.stellard@amd.com> | 2012-07-25 08:27:50 -0400 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2012-07-27 17:08:08 +0000 |
| commit | c424975572af2edd46863e5bb9fe3c51c96b4f9b (patch) | |
| tree | 3c14f76b204b3da3ac067d2d06d3c5fe73cdf4bc /src/gallium | |
| parent | bdda1cb914a291f42cb2221b42e922f22dccb777 (diff) | |
| download | external_mesa3d-c424975572af2edd46863e5bb9fe3c51c96b4f9b.zip external_mesa3d-c424975572af2edd46863e5bb9fe3c51c96b4f9b.tar.gz external_mesa3d-c424975572af2edd46863e5bb9fe3c51c96b4f9b.tar.bz2 | |
radeon/llvm: Add i1 registers for SI.
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeon/SIISelLowering.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/SIISelLowering.cpp b/src/gallium/drivers/radeon/SIISelLowering.cpp index 7940085..23eb4f8 100644 --- a/src/gallium/drivers/radeon/SIISelLowering.cpp +++ b/src/gallium/drivers/radeon/SIISelLowering.cpp @@ -27,6 +27,8 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) : addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass); addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass); addRegisterClass(MVT::i64, &AMDGPU::VReg_64RegClass); + addRegisterClass(MVT::i1, &AMDGPU::SCCRegRegClass); + addRegisterClass(MVT::i1, &AMDGPU::VCCRegRegClass); addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass); addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass); |