diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2012-07-26 08:41:00 -0400 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2012-07-27 17:08:09 +0000 |
| commit | ee0f0f03c6c174a160e5fb3882ec5c03cdfcd163 (patch) | |
| tree | def5f21814a5bab13df7c6343a1e96bce2bcad02 /src/gallium | |
| parent | d4bdd09d4714ae51b9f5675f7f5c678d431061e8 (diff) | |
| download | external_mesa3d-ee0f0f03c6c174a160e5fb3882ec5c03cdfcd163.zip external_mesa3d-ee0f0f03c6c174a160e5fb3882ec5c03cdfcd163.tar.gz external_mesa3d-ee0f0f03c6c174a160e5fb3882ec5c03cdfcd163.tar.bz2 | |
radeon/llvm: Fix VOPC and V_CNDMASK encoding
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/radeon/SIISelLowering.cpp | 4 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/SIInstrFormats.td | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/SIInstrInfo.td | 7 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/SIInstructions.td | 10 |
4 files changed, 13 insertions, 10 deletions
diff --git a/src/gallium/drivers/radeon/SIISelLowering.cpp b/src/gallium/drivers/radeon/SIISelLowering.cpp index 5ce85e1..591968a 100644 --- a/src/gallium/drivers/radeon/SIISelLowering.cpp +++ b/src/gallium/drivers/radeon/SIISelLowering.cpp @@ -179,12 +179,14 @@ void SITargetLowering::LowerSI_INTERP_CONST(MachineInstr *MI, void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB, MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const { - BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMP_LT_F32_e32)) + BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMP_LT_F32_e32), + AMDGPU::VCC) .addOperand(MI->getOperand(1)) .addReg(AMDGPU::SREG_LIT_0); BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CNDMASK_B32)) .addOperand(MI->getOperand(0)) + .addReg(AMDGPU::VCC) .addOperand(MI->getOperand(2)) .addOperand(MI->getOperand(3)); diff --git a/src/gallium/drivers/radeon/SIInstrFormats.td b/src/gallium/drivers/radeon/SIInstrFormats.td index 3d9d474..8f56e21 100644 --- a/src/gallium/drivers/radeon/SIInstrFormats.td +++ b/src/gallium/drivers/radeon/SIInstrFormats.td @@ -100,7 +100,7 @@ class SOPK_64 <bits<5> op, string opName, list<dag> pattern> class VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc, string opName, list<dag> pattern> : VOPC < - op, (outs), (ins arc:$src0, vrc:$src1), opName, pattern + op, (ins arc:$src0, vrc:$src1), opName, pattern >; multiclass VOPC_32 <bits<8> op, string opName, list<dag> pattern> { diff --git a/src/gallium/drivers/radeon/SIInstrInfo.td b/src/gallium/drivers/radeon/SIInstrInfo.td index 72f03d2..d71df43 100644 --- a/src/gallium/drivers/radeon/SIInstrInfo.td +++ b/src/gallium/drivers/radeon/SIInstrInfo.td @@ -407,8 +407,8 @@ class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> : let PostEncoderMethod = "VOPPostEncode"; } -class VOPC <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> : - Enc32 <outs, ins, asm, pattern> { +class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> : + Enc32 <(outs VCCReg:$dst), ins, asm, pattern> { bits<9> SRC0; bits<8> VSRC1; @@ -420,8 +420,7 @@ class VOPC <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> : let EncodingType = 15; //SIInstrEncodingType::VOPC let PostEncoderMethod = "VOPPostEncode"; - - let Defs = [VCC]; + let DisableEncoding = "$dst"; } class MIMG_Load_Helper <bits<7> op, string asm> : MIMG < diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td index 01fb81e..544ef20 100644 --- a/src/gallium/drivers/radeon/SIInstructions.td +++ b/src/gallium/drivers/radeon/SIInstructions.td @@ -590,10 +590,12 @@ def S_WAITCNT : SOPP <0x0000000c, (ins i32imm:$simm16), "S_WAITCNT $simm16">; //def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>; /* XXX: No VOP3 version of this instruction yet */ -def V_CNDMASK_B32 : VOP2_Helper < - 0x00000000, VReg_32, AllReg_32, "V_CNDMASK_B32", []> { - let VDST = 0; - let Uses = [VCC]; +def V_CNDMASK_B32 : VOP2 <0x00000000, (outs VReg_32:$dst), + (ins VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1), "V_CNDMASK_B32", + [(set (i32 VReg_32:$dst), + (select VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1))] > { + + let DisableEncoding = "$vcc"; } defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>; defm V_WRITELANE_B32 : VOP2_32 <0x00000002, "V_WRITELANE_B32", []>; |