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| author | Eric Anholt <eric@anholt.net> | 2016-11-11 14:04:42 -0800 |
|---|---|---|
| committer | Emil Velikov <emil.l.velikov@gmail.com> | 2016-11-24 16:34:39 +0000 |
| commit | fd5fe00f7bb672cad9da19329acac88dcc2086f7 (patch) | |
| tree | d8653f6bc40364e6e6b694dbe84ebdd4facb0637 /src/gallium | |
| parent | e3fe51dbeee6f9d7520e99ac83efcc57646a2253 (diff) | |
| download | external_mesa3d-fd5fe00f7bb672cad9da19329acac88dcc2086f7.zip external_mesa3d-fd5fe00f7bb672cad9da19329acac88dcc2086f7.tar.gz external_mesa3d-fd5fe00f7bb672cad9da19329acac88dcc2086f7.tar.bz2 | |
vc4: Fix register class handling of DDX/DDY arguments.
I had this exactly backwards, but apparently the piglit tests were all
landing in r0-r3 anyway.
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
(cherry picked from commit 977d8b526b983c8d19df00af224033389f8ab7c8)
Diffstat (limited to 'src/gallium')
| -rw-r--r-- | src/gallium/drivers/vc4/vc4_register_allocate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/vc4/vc4_register_allocate.c b/src/gallium/drivers/vc4/vc4_register_allocate.c index 6c99b05..ab343ee 100644 --- a/src/gallium/drivers/vc4/vc4_register_allocate.c +++ b/src/gallium/drivers/vc4/vc4_register_allocate.c @@ -247,7 +247,7 @@ vc4_register_allocate(struct vc4_context *vc4, struct vc4_compile *c) case QOP_ROT_MUL: assert(inst->src[0].file == QFILE_TEMP); - class_bits[inst->src[0].index] &= ~CLASS_BIT_R0_R3; + class_bits[inst->src[0].index] &= CLASS_BIT_R0_R3; break; default: |