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authorMatt Turner <mattst88@gmail.com>2016-01-13 11:09:11 -0800
committerMatt Turner <mattst88@gmail.com>2016-01-14 09:28:01 -0800
commitb82e26a6a4d6baf121f44c61c862bfa79ba0d172 (patch)
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parent15640ee77ae601cba33cbbc72256e55e03a363e5 (diff)
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nir: Lower bitfield_extract.
The OpenGL specifications for bitfieldExtract() says: The result will be undefined if <offset> or <bits> is negative, or if the sum of <offset> and <bits> is greater than the number of bits used to store the operand. Therefore passing bits=32, offset=0 is legal and defined in GLSL. But the earlier SM5 ubfe/ibfe opcodes are specified to accept a bitfield width ranging from 0-31. As such, Intel and AMD instructions read only the low 5 bits of the width operand, making them not able to implement the GLSL-specified behavior directly. This commit adds ubfe/ibfe operations from SM5 and a lowering pass for bitfield_extract to to handle the trivial case of <bits> = 32 as bitfieldExtract: bits > 31 ? value : bfe(value, offset, bits) Fixes: ES31-CTS.shader_bitfield_operation.bitfieldExtract.uvec3_0 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92595 Reviewed-by: Connor Abbott <cwabbott0@gmail.com> Tested-by: Marta Lofstedt <marta.lofstedt@intel.com>
Diffstat (limited to 'src/glsl/nir/nir_opcodes.py')
-rw-r--r--src/glsl/nir/nir_opcodes.py31
1 files changed, 31 insertions, 0 deletions
diff --git a/src/glsl/nir/nir_opcodes.py b/src/glsl/nir/nir_opcodes.py
index 3e43438..e79810c 100644
--- a/src/glsl/nir/nir_opcodes.py
+++ b/src/glsl/nir/nir_opcodes.py
@@ -573,6 +573,37 @@ if (mask == 0) {
}
""")
+# SM5 ubfe/ibfe assembly
+opcode("ubfe", 0, tuint,
+ [0, 0, 0], [tuint, tint, tint], "", """
+unsigned base = src0;
+int offset = src1, bits = src2;
+if (bits == 0) {
+ dst = 0;
+} else if (bits < 0 || offset < 0) {
+ dst = 0; /* undefined */
+} else if (offset + bits < 32) {
+ dst = (base << (32 - bits - offset)) >> (32 - bits);
+} else {
+ dst = base >> offset;
+}
+""")
+opcode("ibfe", 0, tint,
+ [0, 0, 0], [tint, tint, tint], "", """
+int base = src0;
+int offset = src1, bits = src2;
+if (bits == 0) {
+ dst = 0;
+} else if (bits < 0 || offset < 0) {
+ dst = 0; /* undefined */
+} else if (offset + bits < 32) {
+ dst = (base << (32 - bits - offset)) >> (32 - bits);
+} else {
+ dst = base >> offset;
+}
+""")
+
+# GLSL bitfieldExtract()
opcode("ubitfield_extract", 0, tuint,
[0, 0, 0], [tuint, tint, tint], "", """
unsigned base = src0;