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| author | Jordan Justen <jordan.l.justen@intel.com> | 2016-03-24 00:29:50 -0700 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2016-03-24 23:49:53 -0700 |
| commit | 7a03fb9ccb3f8a94ec697bc6ebed8c5f859c8b8e (patch) | |
| tree | 98dd079f8fa3411f6f25931679084ae2866a6ea5 /src/intel/genxml/gen9.xml | |
| parent | d353ba8f5fee23e9d9c8165b6cbfaba33e19ace6 (diff) | |
| download | external_mesa3d-7a03fb9ccb3f8a94ec697bc6ebed8c5f859c8b8e.zip external_mesa3d-7a03fb9ccb3f8a94ec697bc6ebed8c5f859c8b8e.tar.gz external_mesa3d-7a03fb9ccb3f8a94ec697bc6ebed8c5f859c8b8e.tar.bz2 | |
genxml: Add L3 Cache Control register definitions
Based on intel_reg.h (5912da45a69923afa1b7f2eb5bb371d848813c41)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'src/intel/genxml/gen9.xml')
| -rw-r--r-- | src/intel/genxml/gen9.xml | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml index 79d3006..bc2639a 100644 --- a/src/intel/genxml/gen9.xml +++ b/src/intel/genxml/gen9.xml @@ -3467,4 +3467,12 @@ <field name="System Instruction Pointer" start="36" end="95" type="offset"/> </instruction> + <register name="L3CNTLREG" length="1" num="0x7034"> + <field name="SLM Enable" start="0" end="0" type="uint"/> + <field name="URB Allocation" start="1" end="7" type="uint"/> + <field name="RO Allocation" start="11" end="17" type="uint"/> + <field name="DC Allocation" start="18" end="24" type="uint"/> + <field name="All Allocation" start="25" end="31" type="uint"/> + </register> + </genxml> |