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| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-09-09 08:57:14 -0700 |
|---|---|---|
| committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-09-12 19:44:05 -0700 |
| commit | 883086500b130e4667108a52bca9f37defcd7564 (patch) | |
| tree | 268ce82c720fc699f2f5ae0b3db44604abb223eb /src/intel/isl | |
| parent | 54db5afd2c8bd3a32658b3fef698c6896f6a297b (diff) | |
| download | external_mesa3d-883086500b130e4667108a52bca9f37defcd7564.zip external_mesa3d-883086500b130e4667108a52bca9f37defcd7564.tar.gz external_mesa3d-883086500b130e4667108a52bca9f37defcd7564.tar.bz2 | |
intel/isl: Allow valign2 for texture-only Y-tiled surfaces on gen7
The restriction that Y-tiled surfaces must have valign == 4 only aplies to
render targets but we were applying it universally. This causes problems
if ISL_FORMAT_R32G32B32_FLOAT is used because it requires valign == 2; this
should be okay because you can't render to that format.
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Diffstat (limited to 'src/intel/isl')
| -rw-r--r-- | src/intel/isl/isl_gen7.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c index 02273f8..f3d8428 100644 --- a/src/intel/isl/isl_gen7.c +++ b/src/intel/isl/isl_gen7.c @@ -354,7 +354,8 @@ gen7_choose_valign_el(const struct isl_device *dev, */ if (isl_surf_usage_is_depth(info->usage) || info->samples > 1 || - tiling == ISL_TILING_Y0) { + ((info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) && + tiling == ISL_TILING_Y0)) { require_valign4 = true; } |