summaryrefslogtreecommitdiffstats
path: root/src/intel/vulkan/anv_image.c
diff options
context:
space:
mode:
authorJason Ekstrand <jason.ekstrand@intel.com>2016-02-24 12:50:31 -0800
committerJason Ekstrand <jason.ekstrand@intel.com>2016-02-27 10:26:14 -0800
commit4b34f2ccb8b97aaf46b2dadb8098463969064753 (patch)
treec67a9ed2f9c1bdedbd2f450b5daef0e84af4ce31 /src/intel/vulkan/anv_image.c
parentbd6470fa6cdc3d969c170d4d9a8aeee12747ecaf (diff)
downloadexternal_mesa3d-4b34f2ccb8b97aaf46b2dadb8098463969064753.zip
external_mesa3d-4b34f2ccb8b97aaf46b2dadb8098463969064753.tar.gz
external_mesa3d-4b34f2ccb8b97aaf46b2dadb8098463969064753.tar.bz2
anv/image: Use isl for filling brw_image_param
Diffstat (limited to 'src/intel/vulkan/anv_image.c')
-rw-r--r--src/intel/vulkan/anv_image.c117
1 files changed, 6 insertions, 111 deletions
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index 72f29f1..46cf241 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -630,8 +630,9 @@ anv_image_view_init(struct anv_image_view *iview,
iview->bo->size - iview->offset, 1);
}
- anv_image_view_fill_image_param(device, iview,
- &iview->storage_image_param);
+ isl_surf_fill_image_param(&device->isl_dev,
+ &iview->storage_image_param,
+ &surface->isl, &isl_view);
if (!device->info.has_llc)
anv_state_clflush(iview->storage_surface_state);
@@ -737,8 +738,9 @@ anv_CreateBufferView(VkDevice _device,
(storage_format == ISL_FORMAT_RAW ? 1 :
format->isl_layout->bs));
- anv_buffer_view_fill_image_param(device, view,
- &view->storage_image_param);
+ isl_buffer_fill_image_param(&device->isl_dev,
+ &view->storage_image_param,
+ view->format, view->range);
} else {
view->storage_surface_state = (struct anv_state){ 0 };
}
@@ -817,110 +819,3 @@ anv_image_get_surface_for_aspect_mask(struct anv_image *image, VkImageAspectFlag
return NULL;
}
}
-
-static void
-image_param_defaults(struct brw_image_param *param)
-{
- memset(param, 0, sizeof *param);
- /* Set the swizzling shifts to all-ones to effectively disable swizzling --
- * See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
- * detailed explanation of these parameters.
- */
- param->swizzling[0] = 0xff;
- param->swizzling[1] = 0xff;
-}
-
-void
-anv_image_view_fill_image_param(struct anv_device *device,
- struct anv_image_view *view,
- struct brw_image_param *param)
-{
- image_param_defaults(param);
-
- const struct isl_surf *surf = &view->image->color_surface.isl;
- const int cpp = isl_format_get_layout(surf->format)->bs;
- const struct isl_extent3d image_align_sa =
- isl_surf_get_image_alignment_sa(surf);
-
- param->size[0] = view->extent.width;
- param->size[1] = view->extent.height;
- if (surf->dim == ISL_SURF_DIM_3D) {
- param->size[2] = view->extent.depth;
- } else {
- param->size[2] = surf->logical_level0_px.array_len - view->base_layer;
- }
-
- isl_surf_get_image_offset_el(surf, view->base_mip, view->base_layer, 0,
- &param->offset[0], &param->offset[1]);
-
- param->stride[0] = cpp;
- param->stride[1] = surf->row_pitch / cpp;
-
- if (device->info.gen < 9 && surf->dim == ISL_SURF_DIM_3D) {
- param->stride[2] = util_align_npot(param->size[0], image_align_sa.w);
- param->stride[3] = util_align_npot(param->size[1], image_align_sa.h);
- } else {
- param->stride[2] = 0;
- param->stride[3] = isl_surf_get_array_pitch_el_rows(surf);
- }
-
- switch (surf->tiling) {
- case ISL_TILING_LINEAR:
- /* image_param_defaults is good enough */
- break;
-
- case ISL_TILING_X:
- /* An X tile is a rectangular block of 512x8 bytes. */
- param->tiling[0] = util_logbase2(512 / cpp);
- param->tiling[1] = util_logbase2(8);
-
- if (device->isl_dev.has_bit6_swizzling) {
- /* Right shifts required to swizzle bits 9 and 10 of the memory
- * address with bit 6.
- */
- param->swizzling[0] = 3;
- param->swizzling[1] = 4;
- }
- break;
-
- case ISL_TILING_Y0:
- /* The layout of a Y-tiled surface in memory isn't really fundamentally
- * different to the layout of an X-tiled surface, we simply pretend that
- * the surface is broken up in a number of smaller 16Bx32 tiles, each
- * one arranged in X-major order just like is the case for X-tiling.
- */
- param->tiling[0] = util_logbase2(16 / cpp);
- param->tiling[1] = util_logbase2(32);
-
- if (device->isl_dev.has_bit6_swizzling) {
- /* Right shift required to swizzle bit 9 of the memory address with
- * bit 6.
- */
- param->swizzling[0] = 3;
- param->swizzling[1] = 0xff;
- }
- break;
-
- default:
- assert(!"Unhandled storage image tiling");
- }
-
- /* 3D textures are arranged in 2D in memory with 2^lod slices per row. The
- * address calculation algorithm (emit_address_calculation() in
- * brw_fs_surface_builder.cpp) handles this as a sort of tiling with
- * modulus equal to the LOD.
- */
- param->tiling[2] = (device->info.gen < 9 && surf->dim == ISL_SURF_DIM_3D ?
- view->base_mip : 0);
-}
-
-void
-anv_buffer_view_fill_image_param(struct anv_device *device,
- struct anv_buffer_view *view,
- struct brw_image_param *param)
-{
- image_param_defaults(param);
-
- param->stride[0] = isl_format_layouts[view->format].bs;
- param->size[0] = view->range / param->stride[0];
-}