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| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-04-28 15:37:39 -0700 |
|---|---|---|
| committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-05-14 13:34:25 -0700 |
| commit | bee160b31be9e09eeab83f62d26ac331f08955fa (patch) | |
| tree | e0446c57d900f30d17419758c3ea3b37c24ded4a /src/intel/vulkan/gen7_pipeline.c | |
| parent | 7be100ac9af52b1ab5e2c34b45aba0d66304d55a (diff) | |
| download | external_mesa3d-bee160b31be9e09eeab83f62d26ac331f08955fa.zip external_mesa3d-bee160b31be9e09eeab83f62d26ac331f08955fa.tar.gz external_mesa3d-bee160b31be9e09eeab83f62d26ac331f08955fa.tar.bz2 | |
i965/fs: Organize prog_data by ksp number rather than SIMD width
The hardware packets organize kernel pointers and GRF start by slots that
don't map directly to dispatch width. This means that all of the state
setup code has to re-arrange the data from prog_data into these slots.
This logic has been duplicated 4 times in the GL driver and one more time
in the Vulkan driver. Let's just put it all in brw_fs.cpp.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/intel/vulkan/gen7_pipeline.c')
| -rw-r--r-- | src/intel/vulkan/gen7_pipeline.c | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/intel/vulkan/gen7_pipeline.c b/src/intel/vulkan/gen7_pipeline.c index d4797c5..285b191 100644 --- a/src/intel/vulkan/gen7_pipeline.c +++ b/src/intel/vulkan/gen7_pipeline.c @@ -375,19 +375,21 @@ genX(graphics_pipeline_create)( POSOFFSET_SAMPLE : POSOFFSET_NONE; ps._32PixelDispatchEnable = false; - ps._16PixelDispatchEnable = pipeline->ps_simd16 != NO_KERNEL; - ps._8PixelDispatchEnable = pipeline->ps_simd8 != NO_KERNEL; + ps._16PixelDispatchEnable = wm_prog_data->dispatch_16; + ps._8PixelDispatchEnable = wm_prog_data->dispatch_8; - ps.DispatchGRFStartRegisterforConstantSetupData0 = pipeline->ps_grf_start0, + ps.DispatchGRFStartRegisterforConstantSetupData0 = + wm_prog_data->base.dispatch_grf_start_reg, ps.DispatchGRFStartRegisterforConstantSetupData1 = 0, - ps.DispatchGRFStartRegisterforConstantSetupData2 = pipeline->ps_grf_start2, + ps.DispatchGRFStartRegisterforConstantSetupData2 = + wm_prog_data->dispatch_grf_start_reg_2, /* Haswell requires the sample mask to be set in this packet as well as * in 3DSTATE_SAMPLE_MASK; the values should match. */ /* _NEW_BUFFERS, _NEW_MULTISAMPLE */ ps.KernelStartPointer1 = 0; - ps.KernelStartPointer2 = pipeline->ps_ksp2; + ps.KernelStartPointer2 = pipeline->ps_ksp0 + wm_prog_data->prog_offset_2; } /* FIXME-GEN7: This needs a lot more work, cf gen7 upload_wm_state(). */ |