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| author | Nanley Chery <nanley.g.chery@intel.com> | 2016-08-04 15:47:23 -0700 |
|---|---|---|
| committer | Nanley Chery <nanley.g.chery@intel.com> | 2016-08-05 09:53:52 -0700 |
| commit | c495c18b24d6ea5ba346709daf673e2037172a39 (patch) | |
| tree | 9354313e4a2f6e5a40a45c199872ece011b6b361 /src/intel/vulkan/gen7_pipeline.c | |
| parent | 21f357b66e5638e3640cf3b3fbaa992dc764c49f (diff) | |
| download | external_mesa3d-c495c18b24d6ea5ba346709daf673e2037172a39.zip external_mesa3d-c495c18b24d6ea5ba346709daf673e2037172a39.tar.gz external_mesa3d-c495c18b24d6ea5ba346709daf673e2037172a39.tar.bz2 | |
anv/gen7_pipeline: Set PixelShaderKillPixel for discards
According to the IVB PRM Vol2 P1, this bit must be set if a pixel shader
contains a discard instruction.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97207
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Diffstat (limited to 'src/intel/vulkan/gen7_pipeline.c')
| -rw-r--r-- | src/intel/vulkan/gen7_pipeline.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/intel/vulkan/gen7_pipeline.c b/src/intel/vulkan/gen7_pipeline.c index 6acdd85..daebc27 100644 --- a/src/intel/vulkan/gen7_pipeline.c +++ b/src/intel/vulkan/gen7_pipeline.c @@ -298,6 +298,7 @@ genX(graphics_pipeline_create)( wm.LineEndCapAntialiasingRegionWidth = 0; /* 0.5 pixels */ wm.LineAntialiasingRegionWidth = 1; /* 1.0 pixels */ wm.PointRasterizationRule = RASTRULE_UPPER_RIGHT; + wm.PixelShaderKillPixel = wm_prog_data->uses_kill; wm.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode; wm.PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth; wm.PixelShaderUsesSourceW = wm_prog_data->uses_src_w; |