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| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-03-04 10:45:24 -0800 |
|---|---|---|
| committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-03-04 12:03:00 -0800 |
| commit | ec18fef88d8a7a1a3541b0d40708a6637412f50e (patch) | |
| tree | 483283fddd7511a789de1dadb93ba5687c2e9758 /src/intel/vulkan/gen7_pipeline.c | |
| parent | fcd8e571851c18a259fdc4ccb34f6ba23f3d29ea (diff) | |
| download | external_mesa3d-ec18fef88d8a7a1a3541b0d40708a6637412f50e.zip external_mesa3d-ec18fef88d8a7a1a3541b0d40708a6637412f50e.tar.gz external_mesa3d-ec18fef88d8a7a1a3541b0d40708a6637412f50e.tar.bz2 | |
anv/pipeline: Set StencilBufferWriteEnable from the pipeline
The hardware docs say that StencilBufferWriteEnable should only be set if
StencilTestEnable is set. It seems reasonable to set them together.
Diffstat (limited to 'src/intel/vulkan/gen7_pipeline.c')
| -rw-r--r-- | src/intel/vulkan/gen7_pipeline.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/intel/vulkan/gen7_pipeline.c b/src/intel/vulkan/gen7_pipeline.c index 22a892b..d563a8c 100644 --- a/src/intel/vulkan/gen7_pipeline.c +++ b/src/intel/vulkan/gen7_pipeline.c @@ -95,6 +95,7 @@ gen7_emit_ds_state(struct anv_pipeline *pipeline, .DoubleSidedStencilEnable = true, .StencilTestEnable = info->stencilTestEnable, + .StencilBufferWriteEnable = info->stencilTestEnable, .StencilFailOp = vk_to_gen_stencil_op[info->front.failOp], .StencilPassDepthPassOp = vk_to_gen_stencil_op[info->front.passOp], .StencilPassDepthFailOp = vk_to_gen_stencil_op[info->front.depthFailOp], |