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| author | Jordan Justen <jordan.l.justen@intel.com> | 2016-03-24 13:05:04 -0700 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2016-03-25 00:19:18 -0700 |
| commit | 8f3c23667433aacf5ad65a699c7ce082f3d6e416 (patch) | |
| tree | 092d42ed4d0e348973c244ab7cb1daa983ad4a1c /src/intel/vulkan/gen8_cmd_buffer.c | |
| parent | 7a03fb9ccb3f8a94ec697bc6ebed8c5f859c8b8e (diff) | |
| download | external_mesa3d-8f3c23667433aacf5ad65a699c7ce082f3d6e416.zip external_mesa3d-8f3c23667433aacf5ad65a699c7ce082f3d6e416.tar.gz external_mesa3d-8f3c23667433aacf5ad65a699c7ce082f3d6e416.tar.bz2 | |
anv: Use genxml register support for L3 Cache config
The programming of the L3 Cache registers should match the previous
manually packed LRI values.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'src/intel/vulkan/gen8_cmd_buffer.c')
| -rw-r--r-- | src/intel/vulkan/gen8_cmd_buffer.c | 33 |
1 files changed, 16 insertions, 17 deletions
diff --git a/src/intel/vulkan/gen8_cmd_buffer.c b/src/intel/vulkan/gen8_cmd_buffer.c index 87b5e34..3fb5c27 100644 --- a/src/intel/vulkan/gen8_cmd_buffer.c +++ b/src/intel/vulkan/gen8_cmd_buffer.c @@ -108,15 +108,10 @@ gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer *cmd_buffer) } #endif -static void -emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm) -{ - anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), - .RegisterOffset = reg, - .DataDWord = imm); -} - -#define GEN8_L3CNTLREG 0x7034 +#define emit_lri(batch, reg, imm) \ + anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), \ + .RegisterOffset = __anv_reg_num(reg), \ + .DataDWord = imm) void genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, bool enable_slm) @@ -127,12 +122,16 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, bool enable_slm) * - src/mesa/drivers/dri/i965/gen7_l3_state.c */ - uint32_t val = enable_slm ? - /* All = 48 ways; URB = 16 ways; DC and RO = 0, SLM = 1 */ - 0x60000021 : - /* All = 48 ways; URB = 48 ways; DC, RO and SLM = 0 */ - 0x60000060; - bool changed = cmd_buffer->state.current_l3_config != val; + uint32_t l3cr_slm, l3cr_noslm; + anv_pack_struct(&l3cr_noslm, GENX(L3CNTLREG), + .URBAllocation = 48, + .AllAllocation = 48); + anv_pack_struct(&l3cr_slm, GENX(L3CNTLREG), + .SLMEnable = 1, + .URBAllocation = 16, + .AllAllocation = 48); + const uint32_t l3cr_val = enable_slm ? l3cr_slm : l3cr_noslm; + bool changed = cmd_buffer->state.current_l3_config != l3cr_val; if (changed) { /* According to the hardware docs, the L3 partitioning can only be changed @@ -157,8 +156,8 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, bool enable_slm) .PostSyncOperation = NoWrite, .CommandStreamerStallEnable = true); - emit_lri(&cmd_buffer->batch, GEN8_L3CNTLREG, val); - cmd_buffer->state.current_l3_config = val; + emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG), l3cr_val); + cmd_buffer->state.current_l3_config = l3cr_val; } } |