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| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-09-12 12:58:38 -0700 |
|---|---|---|
| committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-09-14 17:53:16 -0700 |
| commit | 89a96c8f43370cc84adf92ab32e3de302a1fa1d0 (patch) | |
| tree | b5262dfcae89b3be50ceb341d0f8d8aba70c42ec /src/intel/vulkan/genX_cmd_buffer.c | |
| parent | a814e18c96ccc70473103cf08a675265f0d1b3c9 (diff) | |
| download | external_mesa3d-89a96c8f43370cc84adf92ab32e3de302a1fa1d0.zip external_mesa3d-89a96c8f43370cc84adf92ab32e3de302a1fa1d0.tar.gz external_mesa3d-89a96c8f43370cc84adf92ab32e3de302a1fa1d0.tar.bz2 | |
anv/cmd_buffer: Set the L3 atomic disable mask bit in CHICKEN3 on HSW
Without this bit set, the value in "L3 Atomic Disable" won't get applied by
the hardware so we won't properly get L3 atomic caching.
Fixes dEQP-VK.spirv_assembly.instruction.compute.opatomic.compex and 198 of
the dEQP-VK.image.atomic_operations.* tests on HSW
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Diffstat (limited to 'src/intel/vulkan/genX_cmd_buffer.c')
| -rw-r--r-- | src/intel/vulkan/genX_cmd_buffer.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index b6f93e7..6a84383 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -296,6 +296,7 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, anv_pack_struct(&scratch1, GENX(SCRATCH1), .L3AtomicDisable = !has_dc); anv_pack_struct(&chicken3, GENX(CHICKEN3), + .L3AtomicDisableMask = true, .L3AtomicDisable = !has_dc); emit_lri(&cmd_buffer->batch, GENX(SCRATCH1_num), scratch1); emit_lri(&cmd_buffer->batch, GENX(CHICKEN3_num), chicken3); |