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authorJordan Justen <jordan.l.justen@intel.com>2016-04-02 01:34:40 -0700
committerJordan Justen <jordan.l.justen@intel.com>2016-05-17 13:04:03 -0700
commit8a80af282091e692da7bf4e412918ba2362dfb4f (patch)
tree802322f737c6e4bd3658146f43442dd3962a2f90 /src/intel/vulkan/genX_pipeline.c
parentaa41de080dad1996877fe7faaa8fed5e63d2f622 (diff)
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anv: Port L3 cache programming from i965
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Diffstat (limited to 'src/intel/vulkan/genX_pipeline.c')
-rw-r--r--src/intel/vulkan/genX_pipeline.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index 2a41b2d..918a9a4 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -84,6 +84,8 @@ genX(compute_pipeline_create)(
pipeline->use_repclear = false;
+ anv_setup_pipeline_l3_config(pipeline);
+
const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;