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| author | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-07-22 14:24:06 -0700 |
|---|---|---|
| committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-08-17 14:46:22 -0700 |
| commit | d540864730f2cfa36366a47021554ac00b625b58 (patch) | |
| tree | 0cefa05e5557f5e0a8b733fcdcead8c0f790d2d4 /src/mesa/drivers/dri/i965/brw_blorp.c | |
| parent | 8b02cd44d71563e193029c1cf3f4ddefbe309bb3 (diff) | |
| download | external_mesa3d-d540864730f2cfa36366a47021554ac00b625b58.zip external_mesa3d-d540864730f2cfa36366a47021554ac00b625b58.tar.gz external_mesa3d-d540864730f2cfa36366a47021554ac00b625b58.tar.bz2 | |
i965/blorp: Stop using the miptree in state setup for tex/rt surfaces
This commit movies us from a miptree model to a surf+bo+offset model. In
the GL driver, miptrees are almost always at the start of the bo so the
offset is zero but we don't want to always make that assumption. In the
sort term, gen6 stencil and HiZ will be at an offset but, in the long term,
any Vulkan surface is liable to be at a non-zero offset.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_blorp.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_blorp.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 5d2d1bd..c44a6c9 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -126,8 +126,12 @@ brw_blorp_surface_info_init(struct brw_context *brw, intel_miptree_check_level_layer(mt, level, layer); info->mt = mt; + if (is_render_target) + intel_miptree_used_for_rendering(mt); intel_miptree_get_isl_surf(brw, mt, &info->surf); + info->bo = mt->bo; + info->offset = mt->offset; if (mt->mcs_mt) { intel_miptree_get_aux_isl_surf(brw, mt, &info->aux_surf, @@ -362,7 +366,7 @@ brw_blorp_emit_surface_state(struct brw_context *brw, const uint32_t mocs = is_render_target ? ss_info.rb_mocs : ss_info.tex_mocs; isl_surf_fill_state(&brw->isl_dev, dw, .surf = &surf, .view = &surface->view, - .address = surface->mt->bo->offset64 + surface->bo_offset, + .address = surface->bo->offset64 + surface->offset, .aux_surf = aux_surf, .aux_usage = surface->aux_usage, .aux_address = aux_offset, .mocs = mocs, .clear_color = clear_color, @@ -372,8 +376,8 @@ brw_blorp_emit_surface_state(struct brw_context *brw, /* Emit relocation to surface contents */ drm_intel_bo_emit_reloc(brw->batch.bo, surf_offset + ss_info.reloc_dw * 4, - surface->mt->bo, - dw[ss_info.reloc_dw] - surface->mt->bo->offset64, + surface->bo, + dw[ss_info.reloc_dw] - surface->bo->offset64, read_domains, write_domain); if (aux_surf) { |