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authorKenneth Graunke <kenneth@whitecape.org>2014-11-03 15:34:56 -0800
committerKenneth Graunke <kenneth@whitecape.org>2014-11-03 15:35:25 -0800
commitf7819650979d1fa5339af3eacfa1af1090bf53e8 (patch)
tree2d880dea368272ff95712b55d20b674a3a650616 /src/mesa/drivers/dri/i965/brw_clear.c
parentc31ce2c40cef21be8a0de48bfdf0307e8d4cd424 (diff)
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i965: Disable fast color clears on Skylake for now.
We're not programming the clear values yet, so this won't work. This patch should be (effectively) reverted eventually. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_clear.c')
-rw-r--r--src/mesa/drivers/dri/i965/brw_clear.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index 0e5fef5..1231420 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -242,7 +242,7 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
}
/* Clear color buffers with fast clear or at least rep16 writes. */
- if (brw->gen >= 6 && mask & BUFFER_BITS_COLOR) {
+ if (brw->gen >= 6 && brw->gen < 9 && (mask & BUFFER_BITS_COLOR)) {
if (brw_meta_fast_clear(brw, fb, mask, partial_clear)) {
debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
mask &= ~BUFFER_BITS_COLOR;