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author | Xiang, Haihao <haihao.xiang@intel.com> | 2009-07-13 10:48:43 +0800 |
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committer | Xiang, Haihao <haihao.xiang@intel.com> | 2009-07-13 11:01:13 +0800 |
commit | 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 (patch) | |
tree | 61effe693f29512148ce333209f7e1ee01e5f729 /src/mesa/drivers/dri/i965/brw_clip_point.c | |
parent | f030e2ba17a3b859d30017cfd990552d3af4bad3 (diff) | |
download | external_mesa3d-2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795.zip external_mesa3d-2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795.tar.gz external_mesa3d-2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795.tar.bz2 |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_clip_point.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_clip_point.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_clip_point.c b/src/mesa/drivers/dri/i965/brw_clip_point.c index d17b199..9738299 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_point.c +++ b/src/mesa/drivers/dri/i965/brw_clip_point.c @@ -50,5 +50,7 @@ void brw_emit_point_clip( struct brw_clip_compile *c ) /* Send an empty message to kill the thread: */ brw_clip_tri_alloc_regs(c, 0); + if (c->need_ff_sync) + brw_clip_ff_sync(c); brw_clip_kill_thread(c); } |