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| author | Kenneth Graunke <kenneth@whitecape.org> | 2014-01-13 14:32:56 -0800 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2014-01-20 15:12:23 -0800 |
| commit | 67ebcb4711d7c6d35df03298f065806613a62798 (patch) | |
| tree | 58dc3d20e5297816e53d4a1feee9a9698edca5ad /src/mesa/drivers/dri/i965/brw_clip_state.c | |
| parent | 77425ef91ac2ee3696a303fd9fdb3abb1b6ee368 (diff) | |
| download | external_mesa3d-67ebcb4711d7c6d35df03298f065806613a62798.zip external_mesa3d-67ebcb4711d7c6d35df03298f065806613a62798.tar.gz external_mesa3d-67ebcb4711d7c6d35df03298f065806613a62798.tar.bz2 | |
i965: Use the new drm_intel_bo offset64 field.
libdrm 2.4.52 introduces a new 'uint64_t offset64' field, intended to
replace the old 'unsigned long offset' field. To preserve ABI, libdrm
continues to store the presumed offset in both locations.
On Broadwell, a 64-bit kernel may place BOs at "high" (> 4G) addresses.
However, with a 32-bit userspace, the 'unsigned long offset' field will
only be 32-bit, which is not large enough to hold this value. We need
to use a proper uint64_t (like the kernel does).
Technically, a lot of this code doesn't affect Broadwell, so we could
leave it using the old field. But it makes sense to just switch to the
new, properly typed field.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_clip_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_clip_state.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_clip_state.c b/src/mesa/drivers/dri/i965/brw_clip_state.c index de25b86..0d153c0 100644 --- a/src/mesa/drivers/dri/i965/brw_clip_state.c +++ b/src/mesa/drivers/dri/i965/brw_clip_state.c @@ -132,7 +132,7 @@ brw_upload_clip_unit(struct brw_context *brw) { clip->clip5.guard_band_enable = 1; clip->clip6.clipper_viewport_state_ptr = - (brw->batch.bo->offset + brw->clip.vp_offset) >> 5; + (brw->batch.bo->offset64 + brw->clip.vp_offset) >> 5; /* emit clip viewport relocation */ drm_intel_bo_emit_reloc(brw->batch.bo, |