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| author | Gurchetan Singh <gurchetansingh@chromium.org> | 2016-05-11 13:32:09 -0700 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2016-06-07 15:42:21 -0700 |
| commit | d9546b0c5d1a5136a92276cdd7c14883f0c62737 (patch) | |
| tree | 70aea5ac5a1d7d7ad43fe91b7d2ac604c8a8ae24 /src/mesa/drivers/dri/i965/brw_compiler.c | |
| parent | f39439d1666481bd1316e865eb3507a2a397f346 (diff) | |
| download | external_mesa3d-d9546b0c5d1a5136a92276cdd7c14883f0c62737.zip external_mesa3d-d9546b0c5d1a5136a92276cdd7c14883f0c62737.tar.gz external_mesa3d-d9546b0c5d1a5136a92276cdd7c14883f0c62737.tar.bz2 | |
i965: Integrate precise trig into configuration infrastructure
With this change, to enable precise SIN and COS instructions
on Intel hardware, one can put
<option name="precise_trig" value="true"/>
in the proper drirc file.
V2: Make option name more generic
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Stephane Marchesin <stephane.marchesin@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_compiler.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_compiler.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.c b/src/mesa/drivers/dri/i965/brw_compiler.c index a4855a0..9eda3fc 100644 --- a/src/mesa/drivers/dri/i965/brw_compiler.c +++ b/src/mesa/drivers/dri/i965/brw_compiler.c @@ -103,8 +103,6 @@ brw_compiler_create(void *mem_ctx, const struct brw_device_info *devinfo) brw_fs_alloc_reg_sets(compiler); brw_vec4_alloc_reg_set(compiler); - compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false); - compiler->scalar_stage[MESA_SHADER_VERTEX] = devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS); compiler->scalar_stage[MESA_SHADER_TESS_CTRL] = |