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author | Abdiel Janulgue <abdiel.janulgue@linux.intel.com> | 2015-04-15 13:04:45 +0300 |
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committer | Abdiel Janulgue <abdiel.janulgue@linux.intel.com> | 2015-07-18 16:16:54 +0300 |
commit | 190756482e62cb57e2bc8c798181e5f0171726fb (patch) | |
tree | d7c8cb2ea1e5740f4c527da792c94cb141a0b290 /src/mesa/drivers/dri/i965/brw_context.c | |
parent | 090529af1828817344e0850ef27eebd1f096eb5f (diff) | |
download | external_mesa3d-190756482e62cb57e2bc8c798181e5f0171726fb.zip external_mesa3d-190756482e62cb57e2bc8c798181e5f0171726fb.tar.gz external_mesa3d-190756482e62cb57e2bc8c798181e5f0171726fb.tar.bz2 |
i965: Enable hardware-generated binding tables on render path.
This patch implements the binding table enable command which is also
used to allocate a binding table pool where where hardware-generated
binding table entries are flushed into. Each binding table offset in
the binding table pool is unique per each shader stage that are
enabled within a batch.
Also insert the required brw_tracked_state objects to enable
hw-generated binding tables in normal render path.
v2: - Use MOCS in binding table pool alloc for GEN8
- Fix spurious offset when allocating binding table pool entry
and start from zero instead.
v3: - Include GEN8 fix for spurious offset above.
v4: - Fixup wrong packet length in enable/disable hw-binding table
for GEN8 (Ville).
- Don't invoke HW-binding table disable command when we dont
have resource streamer (Chris).
v5: - Reorder the state cache invalidate flush so it happens in-between
enabling hw-generated binding tables and the previous sw-binding
table GPU state (Chris).
v6: - Do the same fix in v5 for gen7_disable_hw_binding_tables().
- Adhere to coding guidelines and make comments more informative.
Cc: kenneth@whitecape.org
Cc: syrjala@sci.fi
Cc: chris@chris-wilson.co.uk
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_context.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 05cb53b..efcd91a 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -941,6 +941,10 @@ intelDestroyContext(__DRIcontext * driContextPriv) if (brw->wm.base.scratch_bo) drm_intel_bo_unreference(brw->wm.base.scratch_bo); + gen7_reset_hw_bt_pool_offsets(brw); + drm_intel_bo_unreference(brw->hw_bt_pool.bo); + brw->hw_bt_pool.bo = NULL; + drm_intel_gem_context_destroy(brw->hw_ctx); if (ctx->swrast_context) { |