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author | Topi Pohjolainen <topi.pohjolainen@intel.com> | 2016-09-04 11:02:39 +0300 |
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committer | Topi Pohjolainen <topi.pohjolainen@intel.com> | 2016-09-12 08:58:38 +0300 |
commit | 22d9a4824baf0bf89bb8e39025ad01fecb213888 (patch) | |
tree | b2032b96f1549aa0711660506928b811bd9727ae /src/mesa/drivers/dri/i965/brw_context.c | |
parent | 1f51217d99e7eb70a62b2611cd1b70f9b5a40fcf (diff) | |
download | external_mesa3d-22d9a4824baf0bf89bb8e39025ad01fecb213888.zip external_mesa3d-22d9a4824baf0bf89bb8e39025ad01fecb213888.tar.gz external_mesa3d-22d9a4824baf0bf89bb8e39025ad01fecb213888.tar.bz2 |
i965: Track non-compressible sampling of renderbuffers
v3:
- Actually set the flags when needed instead of falsely
overwriting them (Jason).
- Use more generic name for flag (dropped RENDERBUFFER)
- Consult also shader images
v4:
- Consult only lossless compressd shader images
v5:
- Check the existence of renderbuffer before considering
if it matches the given miptree
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_context.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index b880b4f..0e36d47 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -168,6 +168,24 @@ intel_update_framebuffer(struct gl_context *ctx, fb->DefaultGeometry.NumSamples); } +static bool +intel_disable_rb_aux_buffer(struct brw_context *brw, const drm_intel_bo *bo) +{ + const struct gl_framebuffer *fb = brw->ctx.DrawBuffer; + bool found = false; + + for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) { + const struct intel_renderbuffer *irb = + intel_renderbuffer(fb->_ColorDrawBuffers[i]); + + if (irb && irb->mt->bo == bo) { + found = brw->draw_aux_buffer_disabled[i] = true; + } + } + + return found; +} + /* On Gen9 color buffers may be compressed by the hardware (lossless * compression). There are, however, format restrictions and care needs to be * taken that the sampler engine is capable for re-interpreting a buffer with @@ -197,6 +215,10 @@ intel_texture_view_requires_resolve(struct brw_context *brw, _mesa_get_format_name(intel_tex->_Format), _mesa_get_format_name(intel_tex->mt->format)); + if (intel_disable_rb_aux_buffer(brw, intel_tex->mt->bo)) + perf_debug("Sampling renderbuffer with non-compressible format - " + "turning off compression"); + return true; } @@ -220,6 +242,9 @@ intel_update_state(struct gl_context * ctx, GLuint new_state) if (depth_irb) intel_renderbuffer_resolve_hiz(brw, depth_irb); + memset(brw->draw_aux_buffer_disabled, 0, + sizeof(brw->draw_aux_buffer_disabled)); + /* Resolve depth buffer and render cache of each enabled texture. */ int maxEnabledUnit = ctx->Texture._MaxEnabledTexImageUnit; for (int i = 0; i <= maxEnabledUnit; i++) { @@ -262,6 +287,13 @@ intel_update_state(struct gl_context * ctx, GLuint new_state) * surfaces need to be resolved prior to accessing them. */ intel_miptree_resolve_color(brw, tex_obj->mt, 0); + + if (intel_miptree_is_lossless_compressed(brw, tex_obj->mt) && + intel_disable_rb_aux_buffer(brw, tex_obj->mt->bo)) { + perf_debug("Using renderbuffer as shader image - turning " + "off lossless compression"); + } + brw_render_cache_set_check_flush(brw, tex_obj->mt->bo); } } |