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| author | Ben Widawsky <benjamin.widawsky@intel.com> | 2015-06-17 15:50:11 -0700 |
|---|---|---|
| committer | Ben Widawsky <benjamin.widawsky@intel.com> | 2015-06-24 16:37:12 -0700 |
| commit | d1663ccb4c664b0f544ed5d6f0761f3ae2435199 (patch) | |
| tree | b8fa69bdf338b806480a6ab80daa84e267035947 /src/mesa/drivers/dri/i965/brw_context.c | |
| parent | 9f261dc18dba0aa4dc43fc560d343ba9ffd486e9 (diff) | |
| download | external_mesa3d-d1663ccb4c664b0f544ed5d6f0761f3ae2435199.zip external_mesa3d-d1663ccb4c664b0f544ed5d6f0761f3ae2435199.tar.gz external_mesa3d-d1663ccb4c664b0f544ed5d6f0761f3ae2435199.tar.bz2 | |
i965/bxt: Add basic Broxton infrastructure
The thread counts and URB information are all speculative numbers that were
based on some CHV numbers at the time.
v2:
Originally this patch had PCI IDs. I've moved that to a new patch at the end of
the series.
Remove is_cherryview hack.
Add PCI ids. These match the ones defined in the kernel. The only one tested by
us is 0x0a84.
Capitalize the hex string (Mark)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: "Lecluse, Philippe" <Philippe.Lecluse@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_context.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index cf40883..4b51fe5 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -715,6 +715,7 @@ brwCreateContext(gl_api api, brw->is_baytrail = devinfo->is_baytrail; brw->is_haswell = devinfo->is_haswell; brw->is_cherryview = devinfo->is_cherryview; + brw->is_broxton = devinfo->is_broxton; brw->has_llc = devinfo->has_llc; brw->has_hiz = devinfo->has_hiz_and_separate_stencil; brw->has_separate_stencil = devinfo->has_hiz_and_separate_stencil; |