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| author | Ben Widawsky <benjamin.widawsky@intel.com> | 2015-04-16 13:46:57 -0700 |
|---|---|---|
| committer | Ben Widawsky <benjamin.widawsky@intel.com> | 2015-05-18 12:02:18 -0700 |
| commit | 313abbb8ca1f41b28c58571ca8217332d52283c7 (patch) | |
| tree | b13a6735a03d0aa2b8cdd991824c421abc68ef60 /src/mesa/drivers/dri/i965/brw_defines.h | |
| parent | 7f0c7a5f90d084b1fb1e059367856436a19dca5a (diff) | |
| download | external_mesa3d-313abbb8ca1f41b28c58571ca8217332d52283c7.zip external_mesa3d-313abbb8ca1f41b28c58571ca8217332d52283c7.tar.gz external_mesa3d-313abbb8ca1f41b28c58571ca8217332d52283c7.tar.bz2 | |
i965: Add gen8 surface state debug info
AFAICT, none of the old data was wrong (the gen7 decoder), but it wa smissing a
bunch of stuff.
Adds a tick (') to denote the beginning of the surface state for easier reading.
This will be replaced later with some better, but more risky code.
OLD:
0x00007980: 0x23016000: SURF: 2D BRW_SURFACEFORMAT_B8G8R8A8_UNORM
0x00007984: 0x18000000: SURF: offset
0x00007988: 0x00ff00ff: SURF: 256x256 size, 0 mips, 1 slices
0x0000798c: 0x000003ff: SURF: pitch 1024, tiled
0x00007990: 0x00000000: SURF: min array element 0, array extent 1
0x00007994: 0x00000000: SURF: mip base 0
0x00007998: 0x00000000: SURF: x,y offset: 0,0
0x0000799c: 0x09770000: SURF:
0x00007940: 0x231d7000: SURF: 2D BRW_SURFACEFORMAT_R8G8B8A8_UNORM
0x00007944: 0x78000000: SURF: offset
0x00007948: 0x001f001f: SURF: 32x32 size, 0 mips, 1 slices
0x0000794c: 0x0000007f: SURF: pitch 128, tiled
0x00007950: 0x00000000: SURF: min array element 0, array extent 1
0x00007954: 0x00000000: SURF: mip base 0
0x00007958: 0x00000000: SURF: x,y offset: 0,0
0x0000795c: 0x09770000: SURF:
NEW (v1):
0x00007980: 0x23016000: SURF': 2D B8G8R8A8_UNORM VALIGN4 HALIGN4 X-tiled
0x00007984: 0x18000000: SURF: MOCS: 0x18 Base MIP: 0.0 (0 mips) Surface QPitch: 0
0x00007988: 0x00ff00ff: SURF: 256x256 [AUX_NONE]
0x0000798c: 0x000003ff: SURF: 1 slices (depth), pitch: 1024
0x00007990: 0x00000000: SURF: min array element: 0, array extent 1, MULTISAMPLE_1
0x00007994: 0x00000000: SURF: x,y offset: 0,0, min LOD: 0
0x00007998: 0x00000000: SURF: AUX pitch: 0 qpitch: 0
0x0000799c: 0x09770000: SURF: Clear color: ----
0x00007940: 0x231d7000: SURF': 2D R8G8B8A8_UNORM VALIGN4 HALIGN4 Y-tiled
0x00007944: 0x78000000: SURF: MOCS: 0x78 Base MIP: 0 (0 mips) Surface QPitch: ff0000
0x00007948: 0x001f001f: SURF: 32x32 [AUX_NONE]
0x0000794c: 0x0000007f: SURF: 1 slices (depth), pitch: 128
0x00007950: 0x00000000: SURF: min array element: 0, array extent 1, MULTISAMPLE_1
0x00007954: 0x00000000: SURF: x,y offset: 0,0, min LOD: 0
0x00007958: 0x00000000: SURF: AUX pitch: 0 qpitch: 0
0x0000795c: 0x09770000: SURF: Clear color: ----
0x00007920: 0x00007980: BIND0: surface state address
0x00007924: 0x00007940: BIND1: surface state address
v2: Style cleanups (Matt)
Fix aux mode dword 7->6 (Topi)
Use exp2 instead of pow (Matt)
Add dwords 8-12 to the dump
v3: Needed to update the surface format name getter for the change in the first
patch in the series
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Cc: Matt Turner <mattst88@gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_defines.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 16cecc5..8fd5a49 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -530,9 +530,11 @@ #define GEN7_SURFACE_ARYSPC_FULL (0 << 10) #define GEN7_SURFACE_ARYSPC_LOD0 (1 << 10) -/* Surface state DW0 */ +/* Surface state DW1 */ #define GEN8_SURFACE_MOCS_SHIFT 24 #define GEN8_SURFACE_MOCS_MASK INTEL_MASK(30, 24) +#define GEN8_SURFACE_QPITCH_SHIFT 0 +#define GEN8_SURFACE_QPITCH_MASK INTEL_MASK(14, 0) /* Surface state DW2 */ #define BRW_SURFACE_HEIGHT_SHIFT 19 |