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| author | Topi Pohjolainen <topi.pohjolainen@intel.com> | 2015-12-09 14:44:21 +0200 |
|---|---|---|
| committer | Topi Pohjolainen <topi.pohjolainen@intel.com> | 2016-05-12 19:49:22 +0300 |
| commit | 874c5f05dbc8eca2d14a14f32fdd964808c53b7e (patch) | |
| tree | ccde052139ec4f4cfc82eb1a337e2e033a74e4ec /src/mesa/drivers/dri/i965/brw_defines.h | |
| parent | a8544267fd7936885db3b192c85c1b1f488039a4 (diff) | |
| download | external_mesa3d-874c5f05dbc8eca2d14a14f32fdd964808c53b7e.zip external_mesa3d-874c5f05dbc8eca2d14a14f32fdd964808c53b7e.tar.gz external_mesa3d-874c5f05dbc8eca2d14a14f32fdd964808c53b7e.tar.bz2 | |
i965/gen9: Prepare surface state setup for lossless compression
v2 (Ben): Use combination of msaa_layout and number of samples
instead of introducing explicit type for lossless
compression (intel_miptree_is_lossless_compressed()).
v3 (Ben): Do not set fast claer state in surface state setup.
Moved into brw_postdraw_set_buffers_need_resolve()
using a separate patch.
v4: Support for blorp
v5 (Ben): Re-use gen8_get_aux_mode()
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_defines.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 4696faf..fce510c 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -656,6 +656,7 @@ #define GEN8_SURFACE_AUX_MODE_MCS 1 #define GEN8_SURFACE_AUX_MODE_APPEND 2 #define GEN8_SURFACE_AUX_MODE_HIZ 3 +#define GEN9_SURFACE_AUX_MODE_CCS_E 5 /* Surface state DW7 */ #define GEN9_SURFACE_RT_COMPRESSION_SHIFT 30 |