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| author | Abdiel Janulgue <abdiel.janulgue@linux.intel.com> | 2014-11-11 16:02:14 +0200 |
|---|---|---|
| committer | Abdiel Janulgue <abdiel.janulgue@linux.intel.com> | 2015-12-07 14:58:12 +0200 |
| commit | b19546abf386268e06464624bd6638cf61e595b6 (patch) | |
| tree | 53bf37432f6fc7529baa4734b2fcaf53f7fe9d29 /src/mesa/drivers/dri/i965/brw_defines.h | |
| parent | 9214664aed1f7a87dc0d37c966e9fe3cee2753bf (diff) | |
| download | external_mesa3d-b19546abf386268e06464624bd6638cf61e595b6.zip external_mesa3d-b19546abf386268e06464624bd6638cf61e595b6.tar.gz external_mesa3d-b19546abf386268e06464624bd6638cf61e595b6.tar.bz2 | |
i965: Add defines for gather push constants
v2 (Francisco Jerez):
- Rename HSW_GATHER_CONSTANTS_RESERVED to HSW_GATHER_POOL_ALLOC_MUST_BE_ONE.
- Rename BRW_GATHER_* prefix to HSW_GATHER_CONSTANT_*.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_defines.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index a511d5c..97ef6d4 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -2565,6 +2565,25 @@ enum brw_wm_barycentric_interp_mode { #define _3DSTATE_CONSTANT_HS 0x7819 /* GEN7+ */ #define _3DSTATE_CONSTANT_DS 0x781A /* GEN7+ */ +/* Resource streamer gather constants */ +#define _3DSTATE_GATHER_POOL_ALLOC 0x791A /* GEN7.5+ */ +#define HSW_GATHER_POOL_ALLOC_MUST_BE_ONE (3 << 4) /* GEN7.5 only */ + +#define _3DSTATE_GATHER_CONSTANT_VS 0x7834 /* GEN7.5+ */ +#define _3DSTATE_GATHER_CONSTANT_GS 0x7835 +#define _3DSTATE_GATHER_CONSTANT_HS 0x7836 +#define _3DSTATE_GATHER_CONSTANT_DS 0x7837 +#define _3DSTATE_GATHER_CONSTANT_PS 0x7838 +#define HSW_GATHER_CONSTANT_ENABLE (1 << 11) +#define HSW_GATHER_CONSTANT_BUFFER_VALID_SHIFT 16 +#define HSW_GATHER_CONSTANT_BUFFER_VALID_MASK INTEL_MASK(31, 16) +#define HSW_GATHER_CONSTANT_BINDING_TABLE_BLOCK_SHIFT 12 +#define HSW_GATHER_CONSTANT_BINDING_TABLE_BLOCK_MASK INTEL_MASK(15, 12) +#define HSW_GATHER_CONSTANT_CONST_BUFFER_OFFSET_SHIFT 8 +#define HSW_GATHER_CONSTANT_CONST_BUFFER_OFFSET_MASK INTEL_MASK(15, 8) +#define HSW_GATHER_CONSTANT_CHANNEL_MASK_SHIFT 4 +#define HSW_GATHER_CONSTANT_CHANNEL_MASK_MASK INTEL_MASK(7, 4) + #define _3DSTATE_STREAMOUT 0x781e /* GEN7+ */ /* DW1 */ # define SO_FUNCTION_ENABLE (1 << 31) |