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| author | Kenneth Graunke <kenneth@whitecape.org> | 2015-11-25 17:54:22 -0800 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2015-12-28 13:17:00 -0800 |
| commit | b7793783b3df94880655234bc2a9054eddf01913 (patch) | |
| tree | bb81fb1a60935640aad256e70e2b94975cbff4eb /src/mesa/drivers/dri/i965/brw_defines.h | |
| parent | 6ceabb72eae938570d9aa0ae054bab1df421d79a (diff) | |
| download | external_mesa3d-b7793783b3df94880655234bc2a9054eddf01913.zip external_mesa3d-b7793783b3df94880655234bc2a9054eddf01913.tar.gz external_mesa3d-b7793783b3df94880655234bc2a9054eddf01913.tar.bz2 | |
i965: Relase input URB Handles on Gen7/7.5 when TCS threads finish.
Pre-Broadwell hardware requires us to manually release the ICP Handles
by issuing URB read messages with the "Complete" bit set. We can do
this in pairs to use fewer URB read messages.
Based heavily on work from Chris Forbes.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_defines.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 61bcebd..d013748 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1313,6 +1313,8 @@ enum opcode { TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, TCS_OPCODE_GET_PRIMITIVE_ID, TCS_OPCODE_CREATE_BARRIER_HEADER, + TCS_OPCODE_SRC0_010_IS_ZERO, + TCS_OPCODE_RELEASE_INPUT, TES_OPCODE_GET_PRIMITIVE_ID, TES_OPCODE_CREATE_INPUT_READ_HEADER, |