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| author | Chad Versace <chad.versace@linux.intel.com> | 2013-02-20 19:59:07 -0800 |
|---|---|---|
| committer | Chad Versace <chad.versace@linux.intel.com> | 2013-03-11 16:01:19 -0700 |
| commit | b7262ac7ea650c4416af28097c66fc64f72e3c28 (patch) | |
| tree | 15a65e6161f0c5167c83ca91a713872770f56a1d /src/mesa/drivers/dri/i965/brw_draw.c | |
| parent | 11b8df0c0141c5759025985ba99e782a2dfd720c (diff) | |
| download | external_mesa3d-b7262ac7ea650c4416af28097c66fc64f72e3c28.zip external_mesa3d-b7262ac7ea650c4416af28097c66fc64f72e3c28.tar.gz external_mesa3d-b7262ac7ea650c4416af28097c66fc64f72e3c28.tar.bz2 | |
i965: Fix typo in doxygen hyperlink
s/brw_state_upload/brw_upload_state/
Found because the link was broken.
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_draw.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_draw.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 9c96f69..e408185 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -436,7 +436,7 @@ static bool brw_try_draw_prims( struct gl_context *ctx, intel_prepare_render(intel); - /* This workaround has to happen outside of brw_state_upload() because it + /* This workaround has to happen outside of brw_upload_state() because it * may flush the batchbuffer for a blit, affecting the state flags. */ brw_workaround_depthstencil_alignment(brw); |