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author | Francisco Jerez <currojerez@riseup.net> | 2015-03-19 15:44:24 +0200 |
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committer | Francisco Jerez <currojerez@riseup.net> | 2015-03-20 17:01:35 +0200 |
commit | a902a5d6ba921ab006496aeecab0f68bca7ffb09 (patch) | |
tree | 6453d2f3113b045ad9f5f18673727a618fa599cb /src/mesa/drivers/dri/i965/brw_eu.h | |
parent | fd149628e142af769c1c0ec037bc297d8a3e871f (diff) | |
download | external_mesa3d-a902a5d6ba921ab006496aeecab0f68bca7ffb09.zip external_mesa3d-a902a5d6ba921ab006496aeecab0f68bca7ffb09.tar.gz external_mesa3d-a902a5d6ba921ab006496aeecab0f68bca7ffb09.tar.bz2 |
i965: Factor out logic to build a send message instruction with indirect descriptor.
This is going to be useful because the Gen7+ uniform and varying pull
constant, texturing, typed and untyped surface read, write, and atomic
generation code on the vec4 and fs back-end all require the same logic
to handle conditionally indirect surface indices. In pseudocode:
| if (surface.file == BRW_IMMEDIATE_VALUE) {
| inst = brw_SEND(p, dst, payload);
| set_descriptor_control_bits(inst, surface, ...);
| } else {
| inst = brw_OR(p, addr, surface, 0);
| set_descriptor_control_bits(inst, ...);
| inst = brw_SEND(p, dst, payload);
| set_indirect_send_descriptor(inst, addr);
| }
This patch abstracts out this frequently recurring pattern so we can
now write:
| inst = brw_send_indirect_message(p, sfid, dst, payload, surface)
| set_descriptor_control_bits(inst, ...);
without worrying about handling the immediate and indirect surface
index cases explicitly.
v2: Rebase. Improve documentatation and commit message. (Topi)
Preserve UW destination type cargo-cult. (Topi, Ken, Matt)
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_eu.h')
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu.h | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h index d9ad5bd..a87787e 100644 --- a/src/mesa/drivers/dri/i965/brw_eu.h +++ b/src/mesa/drivers/dri/i965/brw_eu.h @@ -205,11 +205,6 @@ void brw_set_sampler_message(struct brw_compile *p, unsigned simd_mode, unsigned return_format); -void brw_set_indirect_send_descriptor(struct brw_compile *p, - brw_inst *insn, - unsigned sfid, - struct brw_reg descriptor); - void brw_set_dp_read_message(struct brw_compile *p, brw_inst *insn, unsigned binding_table_index, @@ -242,6 +237,22 @@ void brw_urb_WRITE(struct brw_compile *p, unsigned offset, unsigned swizzle); +/** + * Send message to shared unit \p sfid with a possibly indirect descriptor \p + * desc. If \p desc is not an immediate it will be transparently loaded to an + * address register using an OR instruction. The returned instruction can be + * passed as argument to the usual brw_set_*_message() functions in order to + * specify any additional descriptor bits -- If \p desc is an immediate this + * will be the SEND instruction itself, otherwise it will be the OR + * instruction. + */ +struct brw_inst * +brw_send_indirect_message(struct brw_compile *p, + unsigned sfid, + struct brw_reg dst, + struct brw_reg payload, + struct brw_reg desc); + void brw_ff_sync(struct brw_compile *p, struct brw_reg dest, unsigned msg_reg_nr, |