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| author | Kenneth Graunke <kenneth@whitecape.org> | 2011-05-13 07:49:27 -0700 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2011-05-13 15:19:31 -0700 |
| commit | 17eaff77b09d356aae46c5d89a8eaa67cfa4c1e7 (patch) | |
| tree | 02a9e8751f5d35429d5141a3a34e82d6772a7f94 /src/mesa/drivers/dri/i965/brw_eu_emit.c | |
| parent | 5f5d48671741ebadfcb91a58a1fc13816e19b886 (diff) | |
| download | external_mesa3d-17eaff77b09d356aae46c5d89a8eaa67cfa4c1e7.zip external_mesa3d-17eaff77b09d356aae46c5d89a8eaa67cfa4c1e7.tar.gz external_mesa3d-17eaff77b09d356aae46c5d89a8eaa67cfa4c1e7.tar.bz2 | |
i965: Attempt to un-muddle Gen6 data port message target defines.
These are documented on page 245 of IHD_OS_Vol4_Part2.pdf (the public
Sandybridge documentation/SEND instruction description).
Somebody had the bright idea to reuse gen4/5 defines labelled READ/WRITE
which just happened to be the same values as Render Cache/Sampler Cache.
It turns out that this field has nothing to do with READ/WRITE on
Sandybridge, but rather represents which data port to direct it to.
This was especially confusing in brw_set_dp_read_message, which
used "BRW_MESSAGE_TARGET_DATAPORT_WRITE." In a read function.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_eu_emit.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu_emit.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 859068e..82b7137 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -498,7 +498,7 @@ static void brw_set_dp_write_message( struct brw_context *brw, insn->bits3.dp_render_cache.end_of_thread = end_of_thread; /* We always use the render cache for write messages */ - insn->header.destreg__conditionalmod = BRW_MESSAGE_TARGET_DATAPORT_WRITE; + insn->header.destreg__conditionalmod = GEN6_MESSAGE_TARGET_DP_RENDER_CACHE; } else if (intel->gen == 5) { insn->bits3.dp_write_gen5.binding_table_index = binding_table_index; insn->bits3.dp_write_gen5.msg_control = msg_control; @@ -541,9 +541,9 @@ brw_set_dp_read_message(struct brw_context *brw, uint32_t target_function; if (target_cache == BRW_DATAPORT_READ_TARGET_DATA_CACHE) - target_function = BRW_MESSAGE_TARGET_DATAPORT_READ; /* data cache */ + target_function = GEN6_MESSAGE_TARGET_DP_SAMPLER_CACHE; else - target_function = BRW_MESSAGE_TARGET_DATAPORT_WRITE; /* render cache */ + target_function = GEN6_MESSAGE_TARGET_DP_RENDER_CACHE; insn->bits3.dp_render_cache.binding_table_index = binding_table_index; insn->bits3.dp_render_cache.msg_control = msg_control; |