diff options
| author | Iago Toral Quiroga <itoral@igalia.com> | 2015-03-05 09:43:38 +0100 |
|---|---|---|
| committer | Iago Toral Quiroga <itoral@igalia.com> | 2015-03-09 08:15:13 +0100 |
| commit | a72fb69604711d4f0e0fe49241d2da0311503f6a (patch) | |
| tree | 8ed96d14285d172adc6a8579a3d82855c3de6ddf /src/mesa/drivers/dri/i965/brw_fs.h | |
| parent | 8dcc1f2c10b3dc6ded38e7a6c302f60061ba587c (diff) | |
| download | external_mesa3d-a72fb69604711d4f0e0fe49241d2da0311503f6a.zip external_mesa3d-a72fb69604711d4f0e0fe49241d2da0311503f6a.tar.gz external_mesa3d-a72fb69604711d4f0e0fe49241d2da0311503f6a.tar.bz2 | |
i965/fs: Implement SIMD16 dual source blending.
From the SNB PRM, volume 4, part 1, page 193:
"The dual source render target messages only have SIMD8 forms due to
maximum message length limitations. SIMD16 pixel shaders must send two of
these messages to cover all of the pixels. Each message contains two colors
(4 channels each) for each pixel in the message payload."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82831
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_fs.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index ec77962..ee6ba98 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -370,10 +370,12 @@ public: bool optimize_frontfacing_ternary(nir_alu_instr *instr, const fs_reg &result); - int setup_color_payload(fs_reg *dst, fs_reg color, unsigned components); + int setup_color_payload(fs_reg *dst, fs_reg color, unsigned components, + bool use_2nd_half); void emit_alpha_test(); fs_inst *emit_single_fb_write(fs_reg color1, fs_reg color2, - fs_reg src0_alpha, unsigned components); + fs_reg src0_alpha, unsigned components, + bool use_2nd_half = false); void emit_fb_writes(); void emit_urb_writes(); |