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| author | Francisco Jerez <currojerez@riseup.net> | 2015-08-04 19:04:55 +0300 |
|---|---|---|
| committer | Francisco Jerez <currojerez@riseup.net> | 2015-08-06 14:12:12 +0300 |
| commit | 8f5d0988ea2ccaba7f049f113b652f331524d2a6 (patch) | |
| tree | c86698766eec7f268fc40a8eff912c966783f0b0 /src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | |
| parent | f7ac4ef4eeea737115d0b574fed7ecae46426072 (diff) | |
| download | external_mesa3d-8f5d0988ea2ccaba7f049f113b652f331524d2a6.zip external_mesa3d-8f5d0988ea2ccaba7f049f113b652f331524d2a6.tar.gz external_mesa3d-8f5d0988ea2ccaba7f049f113b652f331524d2a6.tar.bz2 | |
i965: Define virtual instruction to calculate the high 32 bits of a multiply.
This instruction will translate to the MUL/MACH sequence that computes
the high 32-bits of the result of a 64-bit multiply. Before Gen8
integer operations that used the accumulator were limited to 8-wide,
but the SIMD lowering pass can easily be hooked up to sidestep this
limitation, we just need a virtual opcode to represent the MUL/MACH
sequence in the IR.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp index 269bdb5..5445ad5 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp @@ -534,6 +534,7 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry) case BRW_OPCODE_MACH: case BRW_OPCODE_MUL: + case SHADER_OPCODE_MULH: case BRW_OPCODE_ADD: case BRW_OPCODE_OR: case BRW_OPCODE_AND: |