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| author | Francisco Jerez <currojerez@riseup.net> | 2016-05-19 00:10:03 -0700 |
|---|---|---|
| committer | Francisco Jerez <currojerez@riseup.net> | 2016-05-27 23:29:04 -0700 |
| commit | 81bc6de8c0f7faafd0f3b0aee944a14ba3ef0b64 (patch) | |
| tree | 15be42f1cedc34eb105d7d8fb7d0838c5c9a005c /src/mesa/drivers/dri/i965/brw_fs_generator.cpp | |
| parent | 41562eb8f33558f02ff8f53b3094a0e6d54e4c49 (diff) | |
| download | external_mesa3d-81bc6de8c0f7faafd0f3b0aee944a14ba3ef0b64.zip external_mesa3d-81bc6de8c0f7faafd0f3b0aee944a14ba3ef0b64.tar.gz external_mesa3d-81bc6de8c0f7faafd0f3b0aee944a14ba3ef0b64.tar.bz2 | |
i965/ir: Make BROADCAST emit an unmasked single-channel move.
Alternatively we could have extended the current semantics to 32-wide
mode by changing brw_broadcast() to emit multiple indexed MOV
instructions in the generator copying the selected value to all
destination registers, but it seemed rather silly to waste EU cycles
unnecessarily copying the exact same value 32 times in the GRF.
The vstride change in the Align16 path is required to avoid assertions
in validate_reg() since the change causes the execution size of the
MOV and SEL instructions to be equal to the source region width.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_fs_generator.cpp')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 1d7fc6c..3b0717e 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -2023,6 +2023,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) break; case SHADER_OPCODE_BROADCAST: + assert(inst->force_writemask_all); brw_broadcast(p, dst, src[0], src[1]); break; |