diff options
| author | Matt Turner <mattst88@gmail.com> | 2015-04-11 14:51:13 -0700 |
|---|---|---|
| committer | Matt Turner <mattst88@gmail.com> | 2015-04-21 09:24:48 -0700 |
| commit | 8bc49f9536058a8373d3057324e22fcbf79a7d89 (patch) | |
| tree | 4cf99c30d6e54f82a74ac1731314cdb1f6af8fd0 /src/mesa/drivers/dri/i965/brw_fs_generator.cpp | |
| parent | b5a5b63548e9b27a3d0b8ad1b399006c71dcc3c4 (diff) | |
| download | external_mesa3d-8bc49f9536058a8373d3057324e22fcbf79a7d89.zip external_mesa3d-8bc49f9536058a8373d3057324e22fcbf79a7d89.tar.gz external_mesa3d-8bc49f9536058a8373d3057324e22fcbf79a7d89.tar.bz2 | |
i965/fs: Set compression only if writing two registers.
We don't want to set compression control on a SIMD16 instruction
operating on words or smaller.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/brw_fs_generator.cpp')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index af08f9d..397d825 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -1631,7 +1631,10 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) break; case 16: case 32: - brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED); + if (type_sz(inst->dst.type) < sizeof(float)) + brw_set_default_compression_control(p, BRW_COMPRESSION_NONE); + else + brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED); break; default: unreachable("Invalid instruction width"); |